Simulation Results: spi_device/2p

 
15/04/2026 16:33:45 DVSim: v1.30.1 sha: cf700e4 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.98 %
  • code
  • 94.07 %
  • assert
  • 91.99 %
  • func
  • 65.87 %
  • line
  • 99.13 %
  • branch
  • 98.39 %
  • cond
  • 95.74 %
  • toggle
  • 87.74 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 14.560s 3412.262us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.400s 84.585us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 2.130s 93.051us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 16.840s 1468.986us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 9.960s 427.137us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.710s 206.097us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 2.130s 93.051us 1 1 100.00
spi_device_csr_aliasing 9.960s 427.137us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.770s 19.281us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.760s 100.176us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.810s 57.216us 1 1 100.00
mem_parity 1 1 100.00
spi_device_mem_parity 1.230s 26.717us 1 1 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 0.850s 16.378us 1 1 100.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.430s 160.775us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.430s 160.775us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 2.760s 533.813us 1 1 100.00
spi_device_tpm_sts_read 0.750s 22.364us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 25.610s 5286.802us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 6.610s 2167.710us 1 1 100.00
spi_device_flash_all 83.730s 33607.569us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 4.560s 638.940us 1 1 100.00
spi_device_flash_all 83.730s 33607.569us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 4.560s 638.940us 1 1 100.00
spi_device_flash_all 83.730s 33607.569us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 83.730s 33607.569us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 2.400s 470.159us 1 1 100.00
spi_device_flash_all 83.730s 33607.569us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 2.400s 470.159us 1 1 100.00
spi_device_flash_all 83.730s 33607.569us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 2.400s 470.159us 1 1 100.00
spi_device_flash_all 83.730s 33607.569us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 2.400s 470.159us 1 1 100.00
spi_device_flash_all 83.730s 33607.569us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 2.400s 470.159us 1 1 100.00
spi_device_flash_all 83.730s 33607.569us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 4.130s 338.013us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 10.560s 1518.743us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 10.560s 1518.743us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 10.560s 1518.743us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 4.940s 1825.393us 1 1 100.00
spi_device_read_buffer_direct 4.960s 921.560us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 10.560s 1518.743us 1 1 100.00
spi_device_flash_all 83.730s 33607.569us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 83.730s 33607.569us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 83.730s 33607.569us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 5.790s 828.552us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 5.790s 828.552us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 14.560s 3412.262us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 197.600s 33782.971us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 82.810s 25275.246us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.870s 26.005us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.750s 91.270us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 2.490s 134.962us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 2.490s 134.962us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.400s 84.585us 1 1 100.00
spi_device_csr_rw 2.130s 93.051us 1 1 100.00
spi_device_csr_aliasing 9.960s 427.137us 1 1 100.00
spi_device_same_csr_outstanding 2.320s 484.037us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.400s 84.585us 1 1 100.00
spi_device_csr_rw 2.130s 93.051us 1 1 100.00
spi_device_csr_aliasing 9.960s 427.137us 1 1 100.00
spi_device_same_csr_outstanding 2.320s 484.037us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.230s 395.860us 1 1 100.00
spi_device_tl_intg_err 14.930s 1517.306us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 14.930s 1517.306us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 9.250s 5101.793us 1 1 100.00