Simulation Results: sram_ctrl/main

 
15/04/2026 16:33:45 DVSim: v1.30.1 sha: cf700e4 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.04 %
  • code
  • 97.05 %
  • assert
  • 96.46 %
  • func
  • 94.60 %
  • block
  • 96.41 %
  • line
  • 96.77 %
  • branch
  • 95.34 %
  • toggle
  • 96.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
90.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 6.000s 731.739us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 43.248us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 2.000s 53.001us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.000s 74.087us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 18.928us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 705.531us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 2.000s 53.001us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 18.928us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 101.000s 14387.462us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 52.000s 4984.371us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 19.000s 6064.104us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 319.000s 15917.642us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 1075.000s 107450.743us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 23.000s 6440.112us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 38.000s 11461.916us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 27.000s 5819.979us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 4.000s 352.062us 1 1 100.00
sram_ctrl_partial_access_b2b 280.000s 19492.490us 1 1 100.00
max_throughput 1 3 33.33
sram_ctrl_max_throughput 3.000s 666.222us 0 1 0.00
sram_ctrl_throughput_w_partial_write 6.000s 2663.940us 1 1 100.00
sram_ctrl_throughput_w_readback 3.000s 2740.376us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 6.000s 2121.076us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 1529.944us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 1364.000s 871346.320us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 16.327us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 50.397us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 50.397us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 43.248us 1 1 100.00
sram_ctrl_csr_rw 2.000s 53.001us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 18.928us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 23.719us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 43.248us 1 1 100.00
sram_ctrl_csr_rw 2.000s 53.001us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 18.928us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 23.719us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 22.000s 14147.489us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 1413.910us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 219.911us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 1413.910us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 219.911us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 6.000s 2121.076us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 6.000s 2121.076us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 2.000s 53.001us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 27.000s 5819.979us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 27.000s 5819.979us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 27.000s 5819.979us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 38.000s 11461.916us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 5.000s 2787.510us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 22.000s 14147.489us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 4.000s 2768.480us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 6.000s 731.739us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 6.000s 731.739us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 27.000s 5819.979us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 1413.910us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 38.000s 11461.916us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 1413.910us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 1413.910us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 6.000s 731.739us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 1413.910us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 33.000s 7476.537us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (sram_ctrl_base_vseq.sv:329) [sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-*:*], *'b0}) <= *; mask dist {'* :/ * - partial_access_pct, [* : '* - *] :/ partial_access_pct};}) Randomization failed!
sram_ctrl_max_throughput 52404970125113979558833486190524293301287543208985074293747265838505292108773 102
UVM_INFO @ 666221945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 110938669972229380500111742969344279563640700210474138610926023199843894463417 102
UVM_INFO @ 2740376181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---