Simulation Results: sram_ctrl/ret

 
15/04/2026 16:33:45 DVSim: v1.30.1 sha: cf700e4 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.28 %
  • code
  • 83.86 %
  • assert
  • 96.43 %
  • func
  • 93.56 %
  • block
  • 94.44 %
  • line
  • 95.36 %
  • branch
  • 91.17 %
  • toggle
  • 82.23 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
90.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 1.000s 98.294us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 14.820us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 113.417us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 97.396us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 26.363us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 32.709us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 113.417us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 26.363us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 8.000s 1522.463us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 3.000s 112.900us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 8.000s 387.022us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 114.000s 2880.510us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 22.000s 2441.763us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 17.000s 728.079us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 6.000s 2613.358us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 2.000s 38.152us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 1.000s 30.200us 1 1 100.00
sram_ctrl_partial_access_b2b 186.000s 11946.183us 1 1 100.00
max_throughput 1 3 33.33
sram_ctrl_max_throughput 2.000s 22.191us 0 1 0.00
sram_ctrl_throughput_w_partial_write 2.000s 43.700us 1 1 100.00
sram_ctrl_throughput_w_readback 2.000s 80.067us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 8.000s 520.412us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 39.561us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 95.000s 19844.297us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 12.783us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 430.191us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 430.191us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 14.820us 1 1 100.00
sram_ctrl_csr_rw 1.000s 113.417us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 26.363us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 16.021us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 14.820us 1 1 100.00
sram_ctrl_csr_rw 1.000s 113.417us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 26.363us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 16.021us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 345.890us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 379.226us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 142.552us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 379.226us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 142.552us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 8.000s 520.412us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 8.000s 520.412us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 113.417us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 2.000s 38.152us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 2.000s 38.152us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 2.000s 38.152us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 6.000s 2613.358us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 2.000s 176.475us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 345.890us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 1.000s 151.169us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 1.000s 98.294us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 1.000s 98.294us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 2.000s 38.152us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 379.226us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 6.000s 2613.358us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 379.226us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 379.226us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 1.000s 98.294us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 379.226us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 51.000s 5042.669us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (sram_ctrl_base_vseq.sv:329) [sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-*:*], *'b0}) <= *; mask dist {'* :/ * - partial_access_pct, [* : '* - *] :/ partial_access_pct};}) Randomization failed!
sram_ctrl_max_throughput 24146504640451508053263980423095023136715977566564826834133055595662232473601 102
UVM_INFO @ 22191014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 96581759162016402679017704486847187768036993269802360504732594352889026312748 102
UVM_INFO @ 80067481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---