Simulation Results: sysrst_ctrl

 
15/04/2026 16:33:45 DVSim: v1.30.1 sha: cf700e4 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.02 %
  • code
  • 92.16 %
  • assert
  • 91.38 %
  • func
  • 71.52 %
  • line
  • 96.63 %
  • branch
  • 97.00 %
  • cond
  • 94.11 %
  • toggle
  • 100.00 %
  • FSM
  • 73.08 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 1.970s 2125.622us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 2.360s 2496.010us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 5.370s 2434.174us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 4.150s 2309.086us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 7.980s 4033.516us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 1.740s 2072.171us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 26.480s 39054.019us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 9.150s 2855.867us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 1.730s 2156.076us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 1.740s 2072.171us 1 1 100.00
sysrst_ctrl_csr_aliasing 9.150s 2855.867us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 213.580s 115540.330us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 83.280s 174127.975us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 7.290s 3490.330us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 7.920s 4060.884us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 5.650s 2510.354us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 4.740s 2094.767us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 3.120s 2708.513us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 3.920s 2618.037us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 1.930s 6616.537us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 14.100s 36716.766us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 115.550s 111376.742us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 0.940s 2135.281us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 2.060s 2033.550us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 4.610s 2044.726us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 4.610s 2044.726us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 7.980s 4033.516us 1 1 100.00
sysrst_ctrl_csr_rw 1.740s 2072.171us 1 1 100.00
sysrst_ctrl_csr_aliasing 9.150s 2855.867us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 5.200s 4995.601us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 7.980s 4033.516us 1 1 100.00
sysrst_ctrl_csr_rw 1.740s 2072.171us 1 1 100.00
sysrst_ctrl_csr_aliasing 9.150s 2855.867us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 5.200s 4995.601us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 82.960s 42009.282us 1 1 100.00
sysrst_ctrl_tl_intg_err 7.840s 22397.751us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 7.840s 22397.751us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 8.060s 7111.220us 1 1 100.00