Simulation Results: uart

 
15/04/2026 16:33:45 DVSim: v1.30.1 sha: cf700e4 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.30 %
  • code
  • 95.93 %
  • assert
  • 97.12 %
  • func
  • 59.86 %
  • line
  • 99.17 %
  • branch
  • 97.44 %
  • cond
  • 95.57 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 12.050s 5384.311us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.690s 29.900us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.680s 56.006us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 2.050s 421.362us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.770s 33.578us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.830s 91.398us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.680s 56.006us 1 1 100.00
uart_csr_aliasing 0.770s 33.578us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 5.420s 72072.213us 1 1 100.00
parity 2 2 100.00
uart_smoke 12.050s 5384.311us 1 1 100.00
uart_tx_rx 5.420s 72072.213us 1 1 100.00
parity_error 2 2 100.00
uart_intr 257.480s 214680.745us 1 1 100.00
uart_rx_parity_err 42.540s 55161.954us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 5.420s 72072.213us 1 1 100.00
uart_intr 257.480s 214680.745us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 157.920s 121718.833us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 56.540s 160752.657us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 24.100s 34309.614us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 257.480s 214680.745us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 257.480s 214680.745us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 257.480s 214680.745us 1 1 100.00
perf 1 1 100.00
uart_perf 71.480s 2800.400us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 3.520s 5125.912us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 3.520s 5125.912us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 3.970s 43632.122us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 1.100s 3252.178us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 10.070s 6380.811us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 2.550s 1377.512us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 591.910s 118349.729us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 160.930s 171007.581us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.640s 11.517us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.680s 27.008us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.960s 108.285us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.960s 108.285us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.690s 29.900us 1 1 100.00
uart_csr_rw 0.680s 56.006us 1 1 100.00
uart_csr_aliasing 0.770s 33.578us 1 1 100.00
uart_same_csr_outstanding 0.720s 49.037us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.690s 29.900us 1 1 100.00
uart_csr_rw 0.680s 56.006us 1 1 100.00
uart_csr_aliasing 0.770s 33.578us 1 1 100.00
uart_same_csr_outstanding 0.720s 49.037us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.030s 79.283us 1 1 100.00
uart_tl_intg_err 1.350s 369.085us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.350s 369.085us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 18.430s 1848.589us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = *
uart_noise_filter 52732663417182182095570002243656546030683537994242051361212276440007831498658 77
UVM_ERROR @ 43602722415 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 43603522415 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 43604122415 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 43604722415 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0