Simulation Results: adc_ctrl

 
16/04/2026 00:05:37 DVSim: v1.30.1 sha: b849398 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 70.12 %
  • code
  • 96.23 %
  • assert
  • 95.95 %
  • func
  • 18.19 %
  • line
  • 99.02 %
  • branch
  • 97.65 %
  • cond
  • 92.60 %
  • toggle
  • 100.00 %
  • FSM
  • 91.89 %
Validation stages
V1
100.00%
V2
94.74%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 2.480s 5863.862us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 3.290s 691.129us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.090s 483.166us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 44.700s 51818.396us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 3.110s 726.293us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.160s 402.719us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.090s 483.166us 1 1 100.00
adc_ctrl_csr_aliasing 3.110s 726.293us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 1 1 100.00
adc_ctrl_filters_polled 31.630s 17709.788us 1 1 100.00
filters_polled_fixed 1 1 100.00
adc_ctrl_filters_polled_fixed 32.630s 54797.292us 1 1 100.00
filters_interrupt 1 1 100.00
adc_ctrl_filters_interrupt 8.080s 54683.890us 1 1 100.00
filters_interrupt_fixed 1 1 100.00
adc_ctrl_filters_interrupt_fixed 10.450s 19503.862us 1 1 100.00
filters_wakeup 1 1 100.00
adc_ctrl_filters_wakeup 115.850s 74424.411us 1 1 100.00
filters_wakeup_fixed 1 1 100.00
adc_ctrl_filters_wakeup_fixed 26.650s 52374.658us 1 1 100.00
filters_both 1 1 100.00
adc_ctrl_filters_both 45.780s 28106.103us 1 1 100.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 2.400s 24014.187us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 7.240s 3749.379us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 32.210s 34749.485us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 191.240s 110117.082us 1 1 100.00
stress_all 1 1 100.00
adc_ctrl_stress_all 140.260s 93872.434us 1 1 100.00
alert_test 1 1 100.00
adc_ctrl_alert_test 0.990s 430.790us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 1.430s 300.019us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 2.130s 546.979us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 2.130s 546.979us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 3.290s 691.129us 1 1 100.00
adc_ctrl_csr_rw 1.090s 483.166us 1 1 100.00
adc_ctrl_csr_aliasing 3.110s 726.293us 1 1 100.00
adc_ctrl_same_csr_outstanding 2.720s 2298.379us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 3.290s 691.129us 1 1 100.00
adc_ctrl_csr_rw 1.090s 483.166us 1 1 100.00
adc_ctrl_csr_aliasing 3.110s 726.293us 1 1 100.00
adc_ctrl_same_csr_outstanding 2.720s 2298.379us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 6.930s 4079.217us 1 1 100.00
adc_ctrl_tl_intg_err 6.090s 8896.255us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 6.090s 8896.255us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
adc_ctrl_stress_all_with_rand_reset 4.410s 2192.234us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error
adc_ctrl_clock_gating 22842661180862113250851436093603890361029405798689167150716136436566362156294 332
UVM_INFO @ 24014186627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---