Simulation Results: aes/masked

 
16/04/2026 00:05:37 DVSim: v1.30.1 sha: b849398 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.97 %
  • code
  • 95.21 %
  • assert
  • 98.43 %
  • func
  • 67.28 %
  • block
  • 95.84 %
  • line
  • 97.51 %
  • branch
  • 89.80 %
  • toggle
  • 98.05 %
  • FSM
  • 95.48 %
Validation stages
V1
100.00%
V2
100.00%
V2S
94.44%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 96.122us 1 1 100.00
smoke 1 1 100.00
aes_smoke 4.000s 161.849us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 142.367us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 62.586us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 5.000s 2616.647us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 605.552us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 84.080us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 62.586us 1 1 100.00
aes_csr_aliasing 3.000s 605.552us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 4.000s 161.849us 1 1 100.00
aes_config_error 3.000s 473.035us 1 1 100.00
aes_stress 4.000s 335.557us 1 1 100.00
key_length 3 3 100.00
aes_smoke 4.000s 161.849us 1 1 100.00
aes_config_error 3.000s 473.035us 1 1 100.00
aes_stress 4.000s 335.557us 1 1 100.00
back2back 2 2 100.00
aes_stress 4.000s 335.557us 1 1 100.00
aes_b2b 6.000s 237.388us 1 1 100.00
backpressure 1 1 100.00
aes_stress 4.000s 335.557us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 4.000s 161.849us 1 1 100.00
aes_config_error 3.000s 473.035us 1 1 100.00
aes_stress 4.000s 335.557us 1 1 100.00
aes_alert_reset 5.000s 209.268us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 152.964us 1 1 100.00
aes_config_error 3.000s 473.035us 1 1 100.00
aes_alert_reset 5.000s 209.268us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 4.000s 69.869us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 73.000s 9326.891us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 8.000s 196.081us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 5.000s 209.268us 1 1 100.00
stress 1 1 100.00
aes_stress 4.000s 335.557us 1 1 100.00
sideload 2 2 100.00
aes_stress 4.000s 335.557us 1 1 100.00
aes_sideload 3.000s 152.646us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 113.376us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 16.000s 1263.048us 1 1 100.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 3.000s 88.058us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 80.709us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 196.774us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 196.774us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 142.367us 1 1 100.00
aes_csr_rw 2.000s 62.586us 1 1 100.00
aes_csr_aliasing 3.000s 605.552us 1 1 100.00
aes_same_csr_outstanding 2.000s 86.989us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 142.367us 1 1 100.00
aes_csr_rw 2.000s 62.586us 1 1 100.00
aes_csr_aliasing 3.000s 605.552us 1 1 100.00
aes_same_csr_outstanding 2.000s 86.989us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 5.000s 375.169us 1 1 100.00
fault_inject 3 3 100.00
aes_fi 3.000s 256.000us 1 1 100.00
aes_control_fi 1.000s 62.657us 1 1 100.00
aes_cipher_fi 3.000s 63.290us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 3.000s 248.503us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 3.000s 248.503us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 3.000s 248.503us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 3.000s 248.503us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 358.845us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 6.000s 957.845us 1 1 100.00
aes_tl_intg_err 3.000s 179.822us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 179.822us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 5.000s 209.268us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 248.503us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 248.503us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 4.000s 161.849us 1 1 100.00
aes_stress 4.000s 335.557us 1 1 100.00
aes_alert_reset 5.000s 209.268us 1 1 100.00
aes_core_fi 61.000s 10052.430us 0 1 0.00
sec_cm_gcm_config_sparse 3 4 75.00
aes_gcm_save_restore 3.000s 88.058us 1 1 100.00
aes_config_error 3.000s 473.035us 1 1 100.00
aes_stress 4.000s 335.557us 1 1 100.00
aes_core_fi 61.000s 10052.430us 0 1 0.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 248.503us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 161.665us 1 1 100.00
aes_stress 4.000s 335.557us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 4.000s 335.557us 1 1 100.00
aes_sideload 3.000s 152.646us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 161.665us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 161.665us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 161.665us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 161.665us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 161.665us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 4.000s 335.557us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 4.000s 335.557us 1 1 100.00
sec_cm_main_fsm_sparse 1 1 100.00
aes_fi 3.000s 256.000us 1 1 100.00
sec_cm_main_fsm_redun 4 4 100.00
aes_fi 3.000s 256.000us 1 1 100.00
aes_control_fi 1.000s 62.657us 1 1 100.00
aes_cipher_fi 3.000s 63.290us 1 1 100.00
aes_ctr_fi 2.000s 57.933us 1 1 100.00
sec_cm_cipher_fsm_sparse 1 1 100.00
aes_fi 3.000s 256.000us 1 1 100.00
sec_cm_cipher_fsm_redun 3 3 100.00
aes_fi 3.000s 256.000us 1 1 100.00
aes_control_fi 1.000s 62.657us 1 1 100.00
aes_cipher_fi 3.000s 63.290us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 3.000s 63.290us 1 1 100.00
sec_cm_ctr_fsm_sparse 1 1 100.00
aes_fi 3.000s 256.000us 1 1 100.00
sec_cm_ctr_fsm_redun 3 3 100.00
aes_fi 3.000s 256.000us 1 1 100.00
aes_control_fi 1.000s 62.657us 1 1 100.00
aes_ctr_fi 2.000s 57.933us 1 1 100.00
sec_cm_ghash_fsm_sparse 1 1 100.00
aes_fi 3.000s 256.000us 1 1 100.00
sec_cm_ctrl_sparse 4 4 100.00
aes_fi 3.000s 256.000us 1 1 100.00
aes_control_fi 1.000s 62.657us 1 1 100.00
aes_cipher_fi 3.000s 63.290us 1 1 100.00
aes_ctr_fi 2.000s 57.933us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 5.000s 209.268us 1 1 100.00
sec_cm_main_fsm_local_esc 4 4 100.00
aes_fi 3.000s 256.000us 1 1 100.00
aes_control_fi 1.000s 62.657us 1 1 100.00
aes_cipher_fi 3.000s 63.290us 1 1 100.00
aes_ctr_fi 2.000s 57.933us 1 1 100.00
sec_cm_cipher_fsm_local_esc 4 4 100.00
aes_fi 3.000s 256.000us 1 1 100.00
aes_control_fi 1.000s 62.657us 1 1 100.00
aes_cipher_fi 3.000s 63.290us 1 1 100.00
aes_ctr_fi 2.000s 57.933us 1 1 100.00
sec_cm_ctr_fsm_local_esc 3 3 100.00
aes_fi 3.000s 256.000us 1 1 100.00
aes_control_fi 1.000s 62.657us 1 1 100.00
aes_ctr_fi 2.000s 57.933us 1 1 100.00
sec_cm_ghash_fsm_local_esc 2 2 100.00
aes_fi 3.000s 256.000us 1 1 100.00
aes_ghash_fi 2.000s 78.390us 1 1 100.00
sec_cm_data_reg_local_esc 3 3 100.00
aes_fi 3.000s 256.000us 1 1 100.00
aes_control_fi 1.000s 62.657us 1 1 100.00
aes_cipher_fi 3.000s 63.290us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 29.000s 2689.687us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_core_fi_vseq.sv:70) [aes_core_fi_vseq] wait timeout occurred!
aes_core_fi 36535105218583365687679994204544979237736737301041884177145675221955006620712 144
UVM_INFO @ 10052429972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
aes_stress_all_with_rand_reset 86366569797453893408130607712381171374185782064245356404194348521731704265064 1087
UVM_INFO @ 2689687194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---