Simulation Results: alert_handler

 
16/04/2026 00:05:37 DVSim: v1.30.1 sha: b849398 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.63 %
  • code
  • 92.69 %
  • assert
  • 98.51 %
  • func
  • 80.70 %
  • line
  • 99.71 %
  • branch
  • 98.42 %
  • cond
  • 92.55 %
  • toggle
  • 93.72 %
  • FSM
  • 79.03 %
Validation stages
V1
100.00%
V2
94.74%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 17.250s 1789.329us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 3.580s 327.633us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 6.700s 125.948us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 136.150s 7559.182us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 46.420s 551.428us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 4.440s 202.373us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 6.700s 125.948us 1 1 100.00
alert_handler_csr_aliasing 46.420s 551.428us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 143.260s 25662.834us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 12.230s 314.794us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 1805.900s 148350.418us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 20.200s 483.990us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 17.250s 1789.329us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 40.880s 4268.941us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 31.400s 809.380us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 81.400s 3171.917us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 859.500s 99328.916us 1 1 100.00
alert_handler_lpg_stub_clk 873.640s 87563.770us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 2174.970s 409378.903us 1 1 100.00
alert_handler_entropy_stress_test 1 1 100.00
alert_handler_entropy_stress 5.350s 472.641us 1 1 100.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 2.950s 160.153us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.160s 7.190us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 7.670s 655.402us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 7.670s 655.402us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 3.580s 327.633us 1 1 100.00
alert_handler_csr_rw 6.700s 125.948us 1 1 100.00
alert_handler_csr_aliasing 46.420s 551.428us 1 1 100.00
alert_handler_same_csr_outstanding 13.060s 3143.323us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 3.580s 327.633us 1 1 100.00
alert_handler_csr_rw 6.700s 125.948us 1 1 100.00
alert_handler_csr_aliasing 46.420s 551.428us 1 1 100.00
alert_handler_same_csr_outstanding 13.060s 3143.323us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 194.160s 19098.273us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 194.160s 19098.273us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 194.160s 19098.273us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 194.160s 19098.273us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 188.990s 8310.470us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 20.430s 8590.957us 1 1 100.00
alert_handler_tl_intg_err 1.910s 36.926us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 1.910s 36.926us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 194.160s 19098.273us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 17.250s 1789.329us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 17.250s 1789.329us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 17.250s 1789.329us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 17.250s 1789.329us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 20.200s 483.990us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 859.500s 99328.916us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 20.200s 483.990us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1805.900s 148350.418us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1805.900s 148350.418us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 20.430s 8590.957us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 20.430s 8590.957us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 20.430s 8590.957us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 20.430s 8590.957us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 20.430s 8590.957us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 20.430s 8590.957us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 20.430s 8590.957us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 20.430s 8590.957us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 20.430s 8590.957us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
alert_handler_stress_all_with_rand_reset 348.110s 21687.678us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state
alert_handler_ping_timeout 66765287542411550703166237783973137759853125649593608911725301106913511524553 99
UVM_INFO @ 3171916943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---