Simulation Results: chip

 
16/04/2026 00:05:37 DVSim: v1.30.1 sha: b849398 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 72.32 %
  • code
  • 84.98 %
  • assert
  • 97.37 %
  • func
  • 34.61 %
  • line
  • 94.18 %
  • branch
  • 93.63 %
  • cond
  • 88.71 %
  • toggle
  • 91.22 %
  • FSM
  • 57.14 %
Validation stages
V1
94.44%
V2
77.70%
V2S
100.00%
V3
65.38%
unmapped
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 141.790s 3092.027us 1 1 100.00
chip_sw_example_rom 78.980s 2461.086us 1 1 100.00
chip_sw_example_manufacturer 143.410s 2713.369us 1 1 100.00
chip_sw_example_concurrency 179.480s 3023.535us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 168.400s 4846.705us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 204.680s 3974.178us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 4819.060s 58870.616us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 3502.360s 26152.896us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
chip_csr_mem_rw_with_rand_reset 73.230s 2313.781us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 3502.360s 26152.896us 1 1 100.00
chip_csr_rw 204.680s 3974.178us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 5.970s 45.132us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 297.460s 4071.535us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 297.460s 4071.535us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 297.460s 4071.535us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 373.850s 4387.123us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 373.850s 4387.123us 1 1 100.00
chip_sw_uart_tx_rx_idx1 334.980s 3820.752us 1 1 100.00
chip_sw_uart_tx_rx_idx2 364.770s 4609.442us 1 1 100.00
chip_sw_uart_tx_rx_idx3 374.840s 4191.515us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 373.220s 4191.612us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 1144.090s 8834.237us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 539.700s 8072.148us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 242.300s 6045.403us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 242.300s 6045.403us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 169.910s 3626.539us 1 1 100.00
chip_sw_sleep_pin_wake 0 1 0.00
chip_sw_sleep_pin_wake 152.860s 2775.527us 0 1 0.00
chip_sw_sleep_pin_retention 1 1 100.00
chip_sw_sleep_pin_retention 174.210s 3245.547us 1 1 100.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 1082.270s 16069.384us 1 1 100.00
chip_tap_straps_testunlock0 117.560s 3361.736us 1 1 100.00
chip_tap_straps_rma 189.110s 4246.500us 1 1 100.00
chip_tap_straps_prod 912.120s 14170.621us 1 1 100.00
chip_sw_pattgen_ios 1 1 100.00
chip_sw_pattgen_ios 194.090s 3202.967us 1 1 100.00
chip_sw_sleep_pwm_pulses 1 1 100.00
chip_sw_sleep_pwm_pulses 761.110s 9473.816us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 485.120s 6840.713us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 485.120s 6840.713us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 551.190s 6703.253us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 657.960s 9522.626us 0 1 0.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 356.990s 4247.491us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 568.020s 5995.824us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3787.080s 19103.302us 1 1 100.00
chip_sw_aes_enc_jitter_en 195.970s 3193.239us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 655.940s 6070.855us 1 1 100.00
chip_sw_hmac_enc_jitter_en 189.060s 3000.497us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1065.920s 8187.324us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 161.610s 2596.072us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 360.260s 4732.178us 1 1 100.00
chip_sw_clkmgr_jitter 178.850s 2880.952us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 239.530s 3747.778us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 2 2 100.00
chip_sw_sensor_ctrl_alert 361.550s 5139.024us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 251.300s 5123.018us 1 1 100.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 161.800s 2783.504us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 251.300s 5123.018us 1 1 100.00
chip_sw_smoketest 17 17 100.00
chip_sw_flash_scrambling_smoketest 141.180s 3105.117us 1 1 100.00
chip_sw_aes_smoketest 203.850s 3601.403us 1 1 100.00
chip_sw_aon_timer_smoketest 185.110s 2665.906us 1 1 100.00
chip_sw_clkmgr_smoketest 160.000s 2795.146us 1 1 100.00
chip_sw_csrng_smoketest 138.100s 2788.526us 1 1 100.00
chip_sw_entropy_src_smoketest 963.490s 6895.143us 1 1 100.00
chip_sw_gpio_smoketest 188.960s 3508.195us 1 1 100.00
chip_sw_hmac_smoketest 168.360s 2796.243us 1 1 100.00
chip_sw_kmac_smoketest 177.730s 3035.132us 1 1 100.00
chip_sw_otbn_smoketest 577.910s 5683.205us 1 1 100.00
chip_sw_pwrmgr_smoketest 282.780s 5928.885us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 303.490s 5369.507us 1 1 100.00
chip_sw_rv_plic_smoketest 147.050s 3247.713us 1 1 100.00
chip_sw_rv_timer_smoketest 147.690s 3088.724us 1 1 100.00
chip_sw_rstmgr_smoketest 138.560s 3388.648us 1 1 100.00
chip_sw_sram_ctrl_smoketest 142.240s 2936.036us 1 1 100.00
chip_sw_uart_smoketest 171.040s 3158.441us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 122.570s 2567.216us 1 1 100.00
chip_sw_rom_functests 0 1 0.00
rom_keymgr_functest 339.110s 4525.835us 0 1 0.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 8054.000s 63725.501us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 3063.480s 14946.012us 1 1 100.00
chip_sw_rom_raw_unlock 0 1 0.00
rom_raw_unlock 44.462s 0.000us 0 1 0.00
chip_sw_power_idle_load 0 1 0.00
chip_sw_power_idle_load 226.920s 3558.724us 0 1 0.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 141.260s 2769.984us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 7111.380s 55209.544us 1 1 100.00
chip_sw_inject_scramble_seed 1 1 100.00
chip_sw_inject_scramble_seed 7697.130s 58476.730us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 44.890s 1662.058us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 44.890s 1662.058us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 3502.360s 26152.896us 1 1 100.00
chip_same_csr_outstanding 3197.870s 30459.873us 1 1 100.00
chip_csr_hw_reset 168.400s 4846.705us 1 1 100.00
chip_csr_rw 204.680s 3974.178us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 3502.360s 26152.896us 1 1 100.00
chip_same_csr_outstanding 3197.870s 30459.873us 1 1 100.00
chip_csr_hw_reset 168.400s 4846.705us 1 1 100.00
chip_csr_rw 204.680s 3974.178us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 33.040s 606.661us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 7.060s 49.337us 1 1 100.00
xbar_smoke_large_delays 56.820s 9200.003us 1 1 100.00
xbar_smoke_slow_rsp 48.910s 5223.480us 1 1 100.00
xbar_random_zero_delays 29.250s 484.182us 1 1 100.00
xbar_random_large_delays 64.530s 10645.772us 1 1 100.00
xbar_random_slow_rsp 175.670s 20782.253us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 40.910s 1284.965us 1 1 100.00
xbar_error_and_unmapped_addr 5.860s 47.071us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 5.070s 129.816us 1 1 100.00
xbar_error_and_unmapped_addr 5.860s 47.071us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 34.030s 818.490us 1 1 100.00
xbar_access_same_device_slow_rsp 184.640s 21247.505us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 42.290s 2285.896us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 228.620s 3722.093us 1 1 100.00
xbar_stress_all_with_error 201.330s 8642.818us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 40.480s 471.502us 1 1 100.00
xbar_stress_all_with_reset_error 162.550s 5217.566us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 3063.480s 14946.012us 1 1 100.00
rom_e2e_shutdown_output 1 1 100.00
rom_e2e_shutdown_output 2457.990s 24873.040us 1 1 100.00
rom_e2e_shutdown_exception_c 1 1 100.00
rom_e2e_shutdown_exception_c 2890.390s 15038.054us 1 1 100.00
rom_e2e_boot_policy_valid 0 15 0.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 66.356s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 87.060s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 74.617s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 62.513s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 62.385s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 71.745s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 63.815s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 145.365s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 63.092s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 63.450s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 72.025s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 122.425s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 136.454s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 121.928s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 127.328s 0.000us 0 1 0.00
rom_e2e_sigverify_always 0 15 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 18.100s 10.100us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 17.540s 10.300us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 17.110s 10.280us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 17.430s 10.100us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 18.900s 10.260us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 18.710s 10.280us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 17.090s 10.220us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 18.190s 10.280us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 21.600s 10.280us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 17.230s 10.340us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 18.920s 10.340us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 17.620s 10.360us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 16.780s 10.220us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 19.490s 10.320us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 18.320s 10.180us 0 1 0.00
rom_e2e_asm_init 0 5 0.00
rom_e2e_asm_init_test_unlocked0 73.086s 0.000us 0 1 0.00
rom_e2e_asm_init_dev 15.266s 0.000us 0 1 0.00
rom_e2e_asm_init_prod 11.658s 0.000us 0 1 0.00
rom_e2e_asm_init_prod_end 9.689s 0.000us 0 1 0.00
rom_e2e_asm_init_rma 86.211s 0.000us 0 1 0.00
rom_e2e_keymgr_init 3 3 100.00
rom_e2e_keymgr_init_rom_ext_meas 5916.620s 28475.686us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_no_meas 5689.710s 28668.655us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 5750.850s 29739.692us 1 1 100.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 3139.060s 15971.771us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3087.780s 34933.216us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3087.780s 34933.216us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 215.190s 3375.511us 1 1 100.00
chip_sw_aes_enc_jitter_en 195.970s 3193.239us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 161.860s 2864.522us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 172.160s 3077.468us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_sideload_aes 1641.860s 11165.672us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 229.390s 3479.819us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 303.180s 4711.196us 1 1 100.00
chip_sw_all_escalation_resets 1 1 100.00
chip_sw_all_escalation_resets 420.880s 6260.066us 1 1 100.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 537.620s 5585.435us 1 1 100.00
chip_plic_all_irqs_10 287.420s 4383.087us 1 1 100.00
chip_plic_all_irqs_20 395.640s 4952.097us 1 1 100.00
chip_sw_alert_handler_entropy 1 1 100.00
chip_sw_alert_handler_entropy 178.070s 3035.058us 1 1 100.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 1269.740s 14058.455us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 265.470s 3948.034us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 118.750s 2713.695us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0.000s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 927.970s 7435.833us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 766.600s 6933.667us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 812.800s 8265.145us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 9135.360s 254844.378us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 249.160s 4015.921us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 282.780s 5928.885us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 249.160s 4015.921us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 463.500s 7838.278us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 463.500s 7838.278us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 248.110s 6482.476us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 411.230s 5844.981us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 625.450s 6666.608us 1 1 100.00
chip_sw_aes_idle 172.160s 3077.468us 1 1 100.00
chip_sw_hmac_enc_idle 161.890s 3038.176us 1 1 100.00
chip_sw_kmac_idle 128.610s 2529.839us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 218.110s 3674.205us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 385.940s 4877.506us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 213.910s 4262.609us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 290.060s 4843.166us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 844.360s 10195.637us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 409.160s 4319.121us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 401.510s 5479.105us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 377.820s 3996.346us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 380.430s 5099.818us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 441.060s 4389.420us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 417.100s 5611.734us 1 1 100.00
chip_sw_ast_clk_outputs 551.190s 6703.253us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 311.100s 7400.477us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 377.820s 3996.346us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 380.430s 5099.818us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 356.990s 4247.491us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 568.020s 5995.824us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3787.080s 19103.302us 1 1 100.00
chip_sw_aes_enc_jitter_en 195.970s 3193.239us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 655.940s 6070.855us 1 1 100.00
chip_sw_hmac_enc_jitter_en 189.060s 3000.497us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1065.920s 8187.324us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 161.610s 2596.072us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 360.260s 4732.178us 1 1 100.00
chip_sw_clkmgr_jitter 178.850s 2880.952us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 143.600s 3011.308us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 371.360s 5152.389us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 653.690s 7254.664us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 4022.360s 25914.323us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 185.680s 3433.635us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 149.430s 2772.037us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 618.190s 7133.042us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 193.450s 3527.953us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 381.660s 5553.058us 1 1 100.00
chip_sw_flash_init_reduced_freq 1186.780s 22239.300us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 4946.400s 38261.481us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 551.190s 6703.253us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 1 1 100.00
chip_sw_clkmgr_sleep_frequency 414.760s 4945.479us 1 1 100.00
chip_sw_clkmgr_reset_frequency 1 1 100.00
chip_sw_clkmgr_reset_frequency 265.920s 3691.841us 1 1 100.00
chip_sw_clkmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 420.880s 6260.066us 1 1 100.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 927.970s 7435.833us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 1033.000s 7052.776us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 0 1 0.00
chip_sw_csrng_fuse_en_sw_app_read_test 154.950s 2626.456us 0 1 0.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 457.750s 6781.523us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 142.610s 2767.955us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 1843.840s 12579.969us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 181.820s 2793.610us 1 1 100.00
chip_sw_edn_entropy_reqs 923.130s 8821.282us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 181.820s 2793.610us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 1033.000s 7052.776us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 123.610s 2843.029us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 1221.750s 21686.610us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 602.820s 5555.068us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 568.020s 5995.824us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 366.840s 3687.530us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 356.990s 4247.491us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 3410.060s 44420.306us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 1221.750s 21686.610us 1 1 100.00
chip_sw_flash_idle_low_power 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 230.010s 3773.927us 1 1 100.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_key_derivation 1450.030s 12234.719us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 192.540s 3290.818us 0 1 0.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 3410.060s 44420.306us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 192.540s 3290.818us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 192.540s 3290.818us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_wr_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 192.540s 3290.818us 0 1 0.00
chip_sw_flash_lc_seed_hw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 192.540s 3290.818us 0 1 0.00
chip_sw_flash_lc_escalate_en 1 1 100.00
chip_sw_all_escalation_resets 420.880s 6260.066us 1 1 100.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 240.250s 8241.568us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 513.260s 5082.408us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 483.960s 6546.211us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 483.960s 6546.211us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 141.020s 2509.186us 1 1 100.00
chip_sw_hmac_enc_jitter_en 189.060s 3000.497us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 161.890s 3038.176us 1 1 100.00
chip_sw_hmac_all_configurations 1 1 100.00
chip_sw_hmac_oneshot 945.370s 7251.779us 1 1 100.00
chip_sw_hmac_multistream_mode 1 1 100.00
chip_sw_hmac_multistream 728.230s 5187.526us 1 1 100.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 327.620s 4079.387us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 419.940s 5258.331us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 357.760s 4705.350us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 247.730s 3286.517us 1 1 100.00
chip_sw_keymgr_key_derivation 2 2 100.00
chip_sw_keymgr_key_derivation 1450.030s 12234.719us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1065.920s 8187.324us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1 1 100.00
chip_sw_keymgr_sideload_kmac 1317.710s 9932.215us 1 1 100.00
chip_sw_keymgr_sideload_aes 1 1 100.00
chip_sw_keymgr_sideload_aes 1641.860s 11165.672us 1 1 100.00
chip_sw_keymgr_sideload_otbn 1 1 100.00
chip_sw_keymgr_sideload_otbn 2048.470s 10591.888us 1 1 100.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 199.070s 3195.363us 1 1 100.00
chip_sw_kmac_mode_kmac 217.670s 2709.528us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 161.610s 2596.072us 1 1 100.00
chip_sw_kmac_app_keymgr 1 1 100.00
chip_sw_keymgr_key_derivation 1450.030s 12234.719us 1 1 100.00
chip_sw_kmac_app_lc 1 1 100.00
chip_sw_lc_ctrl_transition 704.820s 12084.300us 1 1 100.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 143.310s 3055.000us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 1566.890s 11207.141us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 128.610s 2529.839us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 303.180s 4711.196us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 1082.270s 16069.384us 1 1 100.00
chip_tap_straps_rma 189.110s 4246.500us 1 1 100.00
chip_tap_straps_prod 912.120s 14170.621us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 140.200s 2323.643us 1 1 100.00
chip_sw_lc_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 704.820s 12084.300us 1 1 100.00
chip_sw_lc_ctrl_transitions 1 1 100.00
chip_sw_lc_ctrl_transition 704.820s 12084.300us 1 1 100.00
chip_sw_lc_ctrl_kmac_req 1 1 100.00
chip_sw_lc_ctrl_transition 704.820s 12084.300us 1 1 100.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_key_derivation_prod 875.700s 8508.750us 1 1 100.00
chip_sw_lc_ctrl_broadcast 19 22 86.36
chip_sw_flash_ctrl_lc_rw_en 192.540s 3290.818us 0 1 0.00
chip_sw_flash_rma_unlocked 3410.060s 44420.306us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 202.920s 3162.603us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 559.110s 7589.679us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 526.890s 5404.511us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 502.400s 7665.568us 0 1 0.00
chip_sw_lc_ctrl_transition 704.820s 12084.300us 1 1 100.00
chip_sw_keymgr_key_derivation 1450.030s 12234.719us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 308.060s 8640.588us 1 1 100.00
chip_sw_sram_ctrl_execution_main 498.060s 7507.814us 1 1 100.00
chip_prim_tl_access 240.250s 8241.568us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 311.100s 7400.477us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 409.160s 4319.121us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 401.510s 5479.105us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 377.820s 3996.346us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 380.430s 5099.818us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 441.060s 4389.420us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 417.100s 5611.734us 1 1 100.00
chip_tap_straps_dev 1082.270s 16069.384us 1 1 100.00
chip_tap_straps_rma 189.110s 4246.500us 1 1 100.00
chip_tap_straps_prod 912.120s 14170.621us 1 1 100.00
chip_rv_dm_lc_disabled 85.650s 3633.352us 0 1 0.00
chip_lc_scrap 3 4 75.00
chip_sw_lc_ctrl_rma_to_scrap 193.610s 3751.998us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 71.900s 3310.593us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 94.490s 3207.373us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 1770.220s 26902.310us 0 1 0.00
chip_lc_test_locked 1 2 50.00
chip_sw_lc_walkthrough_testunlocks 1634.880s 34956.230us 1 1 100.00
chip_rv_dm_lc_disabled 85.650s 3633.352us 0 1 0.00
chip_sw_lc_walkthrough 2 5 40.00
chip_sw_lc_walkthrough_dev 719.040s 11191.156us 0 1 0.00
chip_sw_lc_walkthrough_prod 614.220s 11745.737us 0 1 0.00
chip_sw_lc_walkthrough_prodend 783.440s 11732.836us 1 1 100.00
chip_sw_lc_walkthrough_rma 411.640s 7371.356us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 1634.880s 34956.230us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 2 3 66.67
chip_sw_lc_ctrl_volatile_raw_unlock 72.770s 2822.416us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 60.990s 2267.648us 1 1 100.00
rom_volatile_raw_unlock 45.792s 0.000us 0 1 0.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 3699.540s 16877.083us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3787.080s 19103.302us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 625.450s 6666.608us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 625.450s 6666.608us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 625.450s 6666.608us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 259.350s 3532.846us 1 1 100.00
chip_otp_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 704.820s 12084.300us 1 1 100.00
chip_sw_otp_ctrl_keys 5 5 100.00
chip_sw_flash_init 1221.750s 21686.610us 1 1 100.00
chip_sw_otbn_mem_scramble 259.350s 3532.846us 1 1 100.00
chip_sw_keymgr_key_derivation 1450.030s 12234.719us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 426.080s 5395.540us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 152.840s 3226.224us 1 1 100.00
chip_sw_otp_ctrl_entropy 5 5 100.00
chip_sw_flash_init 1221.750s 21686.610us 1 1 100.00
chip_sw_otbn_mem_scramble 259.350s 3532.846us 1 1 100.00
chip_sw_keymgr_key_derivation 1450.030s 12234.719us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 426.080s 5395.540us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 152.840s 3226.224us 1 1 100.00
chip_sw_otp_ctrl_program 1 1 100.00
chip_sw_lc_ctrl_transition 704.820s 12084.300us 1 1 100.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 374.280s 4665.462us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 140.200s 2323.643us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 5 6 83.33
chip_sw_otp_ctrl_lc_signals_test_unlocked0 202.920s 3162.603us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 559.110s 7589.679us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 526.890s 5404.511us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 502.400s 7665.568us 0 1 0.00
chip_sw_lc_ctrl_transition 704.820s 12084.300us 1 1 100.00
chip_prim_tl_access 240.250s 8241.568us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 240.250s 8241.568us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 823.830s 7082.582us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 1 1 100.00
chip_sw_pwrmgr_full_aon_reset 292.110s 9050.267us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1010.500s 27434.265us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 237.680s 7573.816us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 0 1 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 313.480s 7053.988us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 470.360s 8175.150us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1128.400s 26893.754us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 0 2 0.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 270.840s 5978.461us 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 463.500s 7838.278us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 909.800s 11424.746us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 341.080s 5096.739us 1 1 100.00
chip_sw_pwrmgr_aon_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_full_aon_reset 292.110s 9050.267us 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 320.740s 5164.370us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 750.160s 15010.520us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 346.560s 8204.488us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 292.870s 4867.254us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 269.930s 5605.908us 0 1 0.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 729.210s 8736.557us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 887.190s 12736.785us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1872.660s 24070.537us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 182.510s 3313.281us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 420.880s 6260.066us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 308.060s 8640.588us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 308.060s 8640.588us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 3 4 75.00
chip_sw_pwrmgr_all_reset_reqs 887.190s 12736.785us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 269.930s 5605.908us 0 1 0.00
chip_sw_pwrmgr_wdog_reset 341.080s 5096.739us 1 1 100.00
chip_sw_pwrmgr_smoketest 282.780s 5928.885us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 301.490s 4393.231us 1 1 100.00
chip_sw_rstmgr_cpu_info 1 1 100.00
chip_sw_rstmgr_cpu_info 502.700s 6976.761us 1 1 100.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 281.470s 4202.843us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 1269.740s 14058.455us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 189.710s 3042.579us 1 1 100.00
chip_sw_rstmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 420.880s 6260.066us 1 1 100.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 766.600s 6933.667us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 515.170s 5376.725us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 514.820s 5001.769us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 244.580s 3471.204us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 152.840s 3226.224us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 1 1 100.00
chip_sw_rstmgr_cpu_info 502.700s 6976.761us 1 1 100.00
chip_sw_rv_core_ibex_double_fault 1 1 100.00
chip_sw_rstmgr_cpu_info 502.700s 6976.761us 1 1 100.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 193.120s 4338.246us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 842.870s 13603.638us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 301.490s 4393.231us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 204.840s 3577.761us 0 1 0.00
chip_rv_dm_access_after_wakeup 1 1 100.00
chip_sw_rv_dm_access_after_wakeup 329.500s 5429.744us 1 1 100.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 189.110s 4246.500us 1 1 100.00
chip_rv_dm_lc_disabled 0 1 0.00
chip_rv_dm_lc_disabled 85.650s 3633.352us 0 1 0.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 537.620s 5585.435us 1 1 100.00
chip_plic_all_irqs_10 287.420s 4383.087us 1 1 100.00
chip_plic_all_irqs_20 395.640s 4952.097us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 145.370s 3052.235us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 122.610s 3029.045us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 3063.480s 14946.012us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 449.160s 7357.904us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 224.820s 3062.318us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 227.960s 3645.978us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 164.830s 3457.980us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 426.080s 5395.540us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 360.260s 4732.178us 1 1 100.00
chip_sw_sleep_sram_ret_contents 2 2 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 371.540s 7540.226us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 504.240s 8819.601us 1 1 100.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 498.060s 7507.814us 1 1 100.00
chip_sw_sram_lc_escalation 2 2 100.00
chip_sw_all_escalation_resets 420.880s 6260.066us 1 1 100.00
chip_sw_data_integrity_escalation 485.120s 6840.713us 1 1 100.00
chip_sw_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 729.210s 8736.557us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1070.940s 24746.298us 1 1 100.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 135.990s 3449.481us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 243.780s 3804.748us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 313.960s 4195.010us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 1 1 100.00
chip_sw_sysrst_ctrl_reset 1070.940s 24746.298us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_reset 1 1 100.00
chip_sw_sysrst_ctrl_reset 1070.940s 24746.298us 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2510.380s 20003.550us 1 1 100.00
chip_sw_sysrst_ctrl_flash_wp_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2510.380s 20003.550us 1 1 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 348.120s 6381.808us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3087.780s 34933.216us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 143.090s 3151.154us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 138.820s 3100.434us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 266.720s 3736.981us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 359.250s 4175.847us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 1023.020s 8427.904us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 5521.820s 31781.860us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 1926.920s 12584.543us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 195.880s 3531.741us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 146.960s 2979.174us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 128.400s 2947.900us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 10096.770s 71585.731us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 1075.700s 6922.963us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 417.970s 6837.019us 0 1 0.00
rom_e2e_jtag_debug_dev 160.270s 4284.116us 0 1 0.00
rom_e2e_jtag_debug_rma 159.210s 4435.374us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 79.820s 2927.197us 0 1 0.00
rom_e2e_jtag_inject_dev 70.590s 2722.420us 0 1 0.00
rom_e2e_jtag_inject_rma 61.710s 2205.333us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 65.529s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 1 0.00
chip_sw_clkmgr_jitter_frequency 239.800s 3579.257us 0 1 0.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 307.270s 3385.437us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 563.930s 4144.815us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 747.710s 6407.226us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 211.120s 2586.574us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 623.280s 5692.551us 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 53.370s 2538.613us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 219.310s 3705.568us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 1 1 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 258.190s 6129.680us 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 345.800s 5630.348us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 887.190s 12736.785us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 417.970s 6837.019us 0 1 0.00
rom_e2e_jtag_debug_dev 160.270s 4284.116us 0 1 0.00
rom_e2e_jtag_debug_rma 159.210s 4435.374us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 370.360s 5740.718us 1 1 100.00
chip_sw_plic_alerts 1 1 100.00
chip_sw_all_escalation_resets 420.880s 6260.066us 1 1 100.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 5645.030s 38475.800us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 5645.030s 38475.800us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 197.990s 3634.654us 1 1 100.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 373.850s 4387.123us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 3149.890s 19481.210us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 8 10 80.00
chip_sival_flash_info_access 182.790s 3167.371us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 446.560s 5625.809us 1 1 100.00
chip_sw_otp_ctrl_rot_auth_config 4.790s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 148.000s 2685.444us 1 1 100.00
chip_sw_otp_ctrl_descrambling 183.360s 2798.672us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 258.810s 4276.462us 1 1 100.00
chip_sw_pwrmgr_sleep_wake_5_bug 7.620s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 174.970s 3685.688us 1 1 100.00
ate_bootstrap_flash_erase 6495.610s 44774.636us 1 1 100.00
ate_bootstrap_disjoint 9922.290s 84743.817us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(!$isunknown(pin_wkup_req_o))'
chip_sw_sleep_pin_wake 99407661504225431601520872799928411133638001482197885771426199715973941468456 318
UVM_ERROR @ 2775.527000 us: (pinmux.sv:662) [ASSERT FAILED] AonWkupReqKnownO_A
UVM_INFO @ 2775.527000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_spi_passthrough_collision_vseq.sv:183) virtual_sequencer [chip_sw_spi_passthrough_collision_vseq] Compare mismatch
chip_sw_spi_device_pass_through_collision 13725946655241009592388871616151482926675502985268994638710755086460647146624 322
host_rsp:
-------------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------------
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_flash_ctrl_lc_rw_en 100678365414960993128672464985216897265238112633119214824964954114707772440099 309
UVM_INFO @ 3290.818316 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *
chip_sw_otp_ctrl_lc_signals_rma 31747124095602656078200787259192586995858555323325115106503398494092912677815 342
UVM_INFO @ 7665.568271 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
chip_sw_otp_ctrl_escalation 110549930839934937095434865015908189531583692387149282222340390682909271123698 316
UVM_ERROR @ 3705.567582 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3705.567582 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_csrng_fuse_en_sw_app_read_test 82825939167488324047051646815154012022749025809824519958496345490689911776462 312
UVM_ERROR @ 2626.456468 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2626.456468 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode
chip_sw_otp_ctrl_rot_auth_config 13800316298982951597890463658874653774493945525161063760515190348372657927520 282
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:845) virtual_sequencer [chip_sw_lc_ctrl_scrap_vseq] max attempt reached to get lc status LcExtClockSwitched!
chip_sw_lc_ctrl_rand_to_scrap 29739170144202793979576616942989776670799530300532734462143127814153835475149 313
UVM_INFO @ 26902.310030 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_lc_walkthrough_dev 112844034854069574636229902848457167373789831135559737952857405914493278895006 369
UVM_INFO @ 11191.156495 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 5653628746436450012700600060300685769347786333719447306166951848677787843242 369
UVM_INFO @ 11745.736711 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 31059834517734802860181955930109417708368587281195005370592714233309531146122 341
UVM_INFO @ 7371.355530 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))'
chip_sw_pwrmgr_random_sleep_all_reset_reqs 40351736310053148335977118834642406777801640381913927371625318581827928531876 315
UVM_ERROR @ 5605.908000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 5605.908000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 13150503467204875357482884728384360990123170670598309785754656026005506108308 314
UVM_ERROR @ 5978.461000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 5978.461000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 114913730306560553013854302714722238507322074447922592092375900779956810991957 325
UVM_ERROR @ 7053.988000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7053.988000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 87327647091480016543071831026797725902518910906296897043989189766756975079371 356
UVM_ERROR @ 15010.520000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 15010.520000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aon_timer_wdog_bite_reset 103018068126127721157556946112941384379876874702530706825707009048152941991980 319
UVM_ERROR @ 7838.278000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7838.278000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 55439339366061573461546634592387391212610411255662669575828525425493806250446 332
UVM_INFO @ 34933.215965 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *!
chip_sw_alert_test 95628913907516951351329395694374191379345229877922866648949969260055364264075 307
UVM_INFO @ 3479.818819 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
chip_sw_alert_handler_lpg_sleep_mode_alerts 79084474175428510998434435582175427954782883992046424050748005562813289690409 308
UVM_INFO @ 2713.694759 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job killed!
chip_sw_alert_handler_lpg_sleep_mode_pings 19899992818671562487940938975322767450801832287875732122882417174205198411936 None
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *).
chip_tl_errors 33657137103736468360340129603082733804797339214758283861935001855442267057808 217
TL item was: req: (cip_tl_seq_item@31517) { a_addr: 'h106c8 a_data: 'hf32e3c8f a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'ha a_opcode: 'h4 a_user: 'h19244 d_param: 'h0 d_source: 'ha d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1662.057678 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 43842113019350394434412152384181264471963279617413842777710411645427868160138 224
TL item was: req: (cip_tl_seq_item@31827) { a_addr: 'h10778 a_data: 'hd5eb3e81 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1c a_opcode: 'h4 a_user: 'h1999f d_param: 'h0 d_source: 'h1c d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2313.781124 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_clkmgr_jitter_frequency 40172579152741180146779033082110165996834195353231053417329022330961815417381 343
UVM_INFO @ 3579.257138 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']
chip_sw_pwrmgr_sleep_wake_5_bug 69309190018027239723195927950902166452991121865785808243022821745927563261711 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 76820677120277192938071859320926385400032703654586700608581484059650696067877 None
Another command (pid=371109) is running. Waiting for it to complete on the server (server_pid=241933)...
Another command (pid=403269) is running. Waiting for it to complete on the server (server_pid=241933)...
Another command (pid=403487) is running. Waiting for it to complete on the server (server_pid=241933)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_dev 88125823565511570161861049513913779824467357793762580717223698720891893407947 None
Another command (pid=562902) is running. Waiting for it to complete on the server (server_pid=241933)...
Another command (pid=590905) is running. Waiting for it to complete on the server (server_pid=241933)...
Another command (pid=567773) is running. Waiting for it to complete on the server (server_pid=241933)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod 37546588085087749786403534602612694169020274234077201738336558780470369169826 None
Another command (pid=556859) is running. Waiting for it to complete on the server (server_pid=241933)...
Another command (pid=559041) is running. Waiting for it to complete on the server (server_pid=241933)...
Another command (pid=543133) is running. Waiting for it to complete on the server (server_pid=241933)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 92570244809191312705970999839136176956275780525687746140259153222897865818888 None
Another command (pid=452983) is running. Waiting for it to complete on the server (server_pid=241933)...
Another command (pid=480816) is running. Waiting for it to complete on the server (server_pid=241933)...
Another command (pid=470172) is running. Waiting for it to complete on the server (server_pid=241933)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_rma 38773187362333495906471114152838922721633144445653020042331083339445164300332 None
Another command (pid=452983) is running. Waiting for it to complete on the server (server_pid=241933)...
Another command (pid=480816) is running. Waiting for it to complete on the server (server_pid=241933)...
Another command (pid=467825) is running. Waiting for it to complete on the server (server_pid=241933)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 32577836867312445425436183285113459041454596623044436782859355395097966724953 None
Another command (pid=428078) is running. Waiting for it to complete on the server (server_pid=241933)...
Another command (pid=361341) is running. Waiting for it to complete on the server (server_pid=241933)...
Another command (pid=443457) is running. Waiting for it to complete on the server (server_pid=241933)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_dev 108217478781178617227912066491214400152542509788953890023781862390756863972951 None
Another command (pid=464232) is running. Waiting for it to complete on the server (server_pid=241933)...
Another command (pid=452983) is running. Waiting for it to complete on the server (server_pid=241933)...
Another command (pid=480816) is running. Waiting for it to complete on the server (server_pid=241933)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod 30093776779978922668942549776764636417286543629691587091573208688004008294851 None
Another command (pid=705989) is running. Waiting for it to complete on the server (server_pid=241933)...
Another command (pid=671927) is running. Waiting for it to complete on the server (server_pid=241933)...
Another command (pid=713085) is running. Waiting for it to complete on the server (server_pid=241933)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 9207070599870139505509969014206495910204617565811336708940496071952729917077 None
Another command (pid=464232) is running. Waiting for it to complete on the server (server_pid=241933)...
Another command (pid=452390) is running. Waiting for it to complete on the server (server_pid=241933)...
Another command (pid=468177) is running. Waiting for it to complete on the server (server_pid=241933)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_rma 37939633296822390130308829158093101572699850787171458287805420919865303637921 None
Another command (pid=452390) is running. Waiting for it to complete on the server (server_pid=241933)...
Another command (pid=468177) is running. Waiting for it to complete on the server (server_pid=241933)...
Another command (pid=449020) is running. Waiting for it to complete on the server (server_pid=241933)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 56406435688529809003751874313265555245729017900565883866079658876545930009096 None
Another command (pid=375686) is running. Waiting for it to complete on the server (server_pid=241933)...
Another command (pid=438433) is running. Waiting for it to complete on the server (server_pid=241933)...
Another command (pid=361341) is running. Waiting for it to complete on the server (server_pid=241933)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_dev 48768741880978866353547030316314257520761025772858391164359735955963692869590 None
Another command (pid=641062) is running. Waiting for it to complete on the server (server_pid=241933)...
Another command (pid=642293) is running. Waiting for it to complete on the server (server_pid=241933)...
Another command (pid=621212) is running. Waiting for it to complete on the server (server_pid=241933)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod 60293607445611178940715384173526172942970257409926409424933871994563776986942 None
Another command (pid=612331) is running. Waiting for it to complete on the server (server_pid=241933)...
Another command (pid=682733) is running. Waiting for it to complete on the server (server_pid=241933)...
Another command (pid=687087) is running. Waiting for it to complete on the server (server_pid=241933)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 33137906506442558918420985173424741148222959016161688222400078999035705436060 None
Another command (pid=621212) is running. Waiting for it to complete on the server (server_pid=241933)...
Another command (pid=626551) is running. Waiting for it to complete on the server (server_pid=241933)...
Another command (pid=637030) is running. Waiting for it to complete on the server (server_pid=241933)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_rma 87023934160709377349076441213606320128514099861520013782854640125364923245664 None
Another command (pid=633405) is running. Waiting for it to complete on the server (server_pid=241933)...
Another command (pid=619240) is running. Waiting for it to complete on the server (server_pid=241933)...
Another command (pid=655107) is running. Waiting for it to complete on the server (server_pid=241933)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_test_unlocked0 17346706952130412465218397440996396614499823319159803452330968801213764564769 None
Another command (pid=371109) is running. Waiting for it to complete on the server (server_pid=241933)...
Another command (pid=403269) is running. Waiting for it to complete on the server (server_pid=241933)...
Another command (pid=403487) is running. Waiting for it to complete on the server (server_pid=241933)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_dev 104805795736193977971035372609396126603590029564563894209571974204848344732081 None
Another command (pid=403269) is running. Waiting for it to complete on the server (server_pid=241933)...
Another command (pid=403487) is running. Waiting for it to complete on the server (server_pid=241933)...
Another command (pid=375686) is running. Waiting for it to complete on the server (server_pid=241933)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod 832858368678680755393416703097485907297165156583829054238823742610460967704 None
Another command (pid=444072) is running. Waiting for it to complete on the server (server_pid=241933)...
Another command (pid=428078) is running. Waiting for it to complete on the server (server_pid=241933)...
Another command (pid=361341) is running. Waiting for it to complete on the server (server_pid=241933)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod_end 53151116575921011049298983682163135751657800522874928955733448803761210932428 None
Another command (pid=371109) is running. Waiting for it to complete on the server (server_pid=241933)...
Another command (pid=403269) is running. Waiting for it to complete on the server (server_pid=241933)...
Another command (pid=403487) is running. Waiting for it to complete on the server (server_pid=241933)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_rma 9196512472507923191879303588254192458494144843744383646297382638138418981726 None
Another command (pid=568651) is running. Waiting for it to complete on the server (server_pid=241933)...
Another command (pid=571385) is running. Waiting for it to complete on the server (server_pid=241933)...
Another command (pid=546463) is running. Waiting for it to complete on the server (server_pid=241933)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_volatile_raw_unlock 57777311778748476072901329577170567900170630602481364537536588889413008402503 None
Another command (pid=398853) is running. Waiting for it to complete on the server (server_pid=241933)...
Another command (pid=403487) is running. Waiting for it to complete on the server (server_pid=241933)...
Another command (pid=363287) is running. Waiting for it to complete on the server (server_pid=241933)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_raw_unlock 100250123558861046503811452709253514198029085053428902112580355671022364655494 None
---- STDERR ----
Another command (pid=360098) is running. Waiting for it to complete on the server (server_pid=241933)...
Another command (pid=371109) is running. Waiting for it to complete on the server (server_pid=241933)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 5876262909576123519070624588280310218736303742026409572245789389291832861209 None
Another command (pid=363287) is running. Waiting for it to complete on the server (server_pid=241933)...
Another command (pid=417004) is running. Waiting for it to complete on the server (server_pid=241933)...
Another command (pid=364141) is running. Waiting for it to complete on the server (server_pid=241933)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 148815402542606446357777584496625546416060984704516827176123980577027028220 327
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_test_unlocked0 102586865363055154760108644479916543660588889635863453841435352138022664949191 352
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_dev 31686736259061890239027082423067218793120506527381341496781456770699543110725 319
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 77819225764038331389035696378320163124343927731143699098110713653893194495136 319
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 75896772273581570026734845764718854181513086205173490982199742642526439980817 303
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 77963928282334727465626501148901743384634325736757846510675420346059113589513 303
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 16915847959501079364326767230583835965947124476141197245468381890583562162102 307
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_ERROR @ * us: (cip_base_vseq.sv:649) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch
chip_rv_dm_lc_disabled 16581560716501090195766644264258144507930217956677908835873860581023196032793 225
UVM_INFO @ 3633.351993 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_idle_load 86747120930900688514112016674021343935954132137994793574296517269556585711687 312
UVM_INFO @ 3558.724000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_sleep_load 115643513287815792309147940572016222259368215738622700162785309208535552299912 318
UVM_INFO @ 2769.984000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *
chip_sw_ast_clk_rst_inputs 62278077781158237760987124825597179553306254895585959394055730074548527593740 327
UVM_INFO @ 9522.626296 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 98457597573669592701668846108931128178683400771057073679715141906343270026099 362
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 19635729963359688728152160818716696159565483705040585479794999970803936435836 325
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_dev 115618964143431152879996177487999147593214681051537712968943553023072031514512 364
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_dev 82915812416411652693202872150689686168571695514308226368949013337995786176013 326
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_prod 87632650933289902371320821462144716544578966075070453702709671584835853654420 364
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 40788669664441747240384817405684798348369232628575023824932429416416135615500 365
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_rma 433985249128187341690353525968311983049231430625773685788974553113876965261 368
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod 59408982478545717466556657381630229222079497565117578469434067297549818729290 327
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 31794355929128592790210838354792933678396663841187721143356135752158546994977 326
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_rma 115173510479802235648250282994690938948748429869937659440692195311086726559482 326
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 45325745919554986946765217541996990382189992048691004981426663854747951908936 325
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_dev 113924538458526327120230910123644936223392367528276573204181239787470629794182 325
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_prod 93546759069914909175010835249943082304188964782747058837537988914842789909118 327
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 65628312439144437516310007340492999213461746755396889442526671598075024638955 327
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_rma 6509694993976114852004631269480796524568809549210023553094304546993702628487 326
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)'
rom_keymgr_functest 14534544149143926959904142359711452325012503315179698748218555220846909720012 327
UVM_ERROR @ 4525.834788 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 4525.834788 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---