Simulation Results: clkmgr

 
16/04/2026 00:05:37 DVSim: v1.30.1 sha: b849398 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.33 %
  • code
  • 98.58 %
  • assert
  • 95.48 %
  • func
  • 85.93 %
  • line
  • 99.23 %
  • branch
  • 98.94 %
  • cond
  • 94.73 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.770s 21.265us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.710s 26.146us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.970s 16.013us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 5.760s 776.753us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.340s 114.608us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.510s 124.586us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.970s 16.013us 1 1 100.00
clkmgr_csr_aliasing 1.340s 114.608us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.940s 14.811us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.100s 28.554us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.800s 24.234us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.870s 50.463us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.770s 21.265us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 8.970s 2120.754us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 8.210s 2420.301us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 8.970s 2120.754us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 21.110s 4627.291us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.940s 19.513us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.630s 78.916us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.630s 78.916us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.710s 26.146us 1 1 100.00
clkmgr_csr_rw 0.970s 16.013us 1 1 100.00
clkmgr_csr_aliasing 1.340s 114.608us 1 1 100.00
clkmgr_same_csr_outstanding 1.040s 37.707us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.710s 26.146us 1 1 100.00
clkmgr_csr_rw 0.970s 16.013us 1 1 100.00
clkmgr_csr_aliasing 1.340s 114.608us 1 1 100.00
clkmgr_same_csr_outstanding 1.040s 37.707us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
clkmgr_sec_cm 2.530s 572.599us 1 1 100.00
clkmgr_tl_intg_err 1.950s 241.577us 1 1 100.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 2.240s 494.995us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 2.240s 494.995us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 2.240s 494.995us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 2.240s 494.995us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 2.130s 250.290us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 1.950s 241.577us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 8.970s 2120.754us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 8.210s 2420.301us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 2.240s 494.995us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.940s 33.947us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.810s 15.423us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.980s 22.925us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.920s 72.073us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.730s 22.762us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.970s 16.013us 1 1 100.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 2.530s 572.599us 1 1 100.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.970s 16.013us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.970s 16.013us 1 1 100.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 2.530s 572.599us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 3.850s 1412.720us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 19.020s 3168.503us 1 1 100.00