Simulation Results: csrng

 
16/04/2026 00:05:37 DVSim: v1.30.1 sha: b849398 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.62 %
  • code
  • 92.43 %
  • assert
  • 93.23 %
  • func
  • 80.19 %
  • block
  • 97.15 %
  • line
  • 97.80 %
  • branch
  • 92.84 %
  • toggle
  • 93.37 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
91.67%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 12.000s 36.396us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 1.000s 29.122us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 14.371us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 24.000s 1127.704us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 3.000s 74.385us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 2.000s 18.703us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 14.371us 1 1 100.00
csrng_csr_aliasing 3.000s 74.385us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 4.000s 68.518us 1 1 100.00
alerts 1 1 100.00
csrng_alert 11.000s 659.963us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 27.848us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 6.000s 383.174us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 6.000s 383.174us 0 1 0.00
stress_all 1 1 100.00
csrng_stress_all 391.000s 10637.973us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 1.000s 15.274us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 55.859us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 10.000s 484.895us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 10.000s 484.895us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 1.000s 29.122us 1 1 100.00
csrng_csr_rw 2.000s 14.371us 1 1 100.00
csrng_csr_aliasing 3.000s 74.385us 1 1 100.00
csrng_same_csr_outstanding 18.000s 50.485us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 1.000s 29.122us 1 1 100.00
csrng_csr_rw 2.000s 14.371us 1 1 100.00
csrng_csr_aliasing 3.000s 74.385us 1 1 100.00
csrng_same_csr_outstanding 18.000s 50.485us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 16.000s 42.024us 1 1 100.00
csrng_tl_intg_err 6.000s 191.974us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_regwen 30.000s 32.935us 1 1 100.00
csrng_csr_rw 2.000s 14.371us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 11.000s 659.963us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 391.000s 10637.973us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 4.000s 68.518us 1 1 100.00
csrng_err 2.000s 27.848us 1 1 100.00
csrng_sec_cm 16.000s 42.024us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 4.000s 68.518us 1 1 100.00
csrng_err 2.000s 27.848us 1 1 100.00
csrng_sec_cm 16.000s 42.024us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 4.000s 68.518us 1 1 100.00
csrng_err 2.000s 27.848us 1 1 100.00
csrng_sec_cm 16.000s 42.024us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 4.000s 68.518us 1 1 100.00
csrng_err 2.000s 27.848us 1 1 100.00
csrng_sec_cm 16.000s 42.024us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 4.000s 68.518us 1 1 100.00
csrng_err 2.000s 27.848us 1 1 100.00
csrng_sec_cm 16.000s 42.024us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 11.000s 659.963us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 4.000s 68.518us 1 1 100.00
csrng_err 2.000s 27.848us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 391.000s 10637.973us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 11.000s 659.963us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 6.000s 191.974us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 4.000s 68.518us 1 1 100.00
csrng_err 2.000s 27.848us 1 1 100.00
csrng_sec_cm 16.000s 42.024us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 4.000s 68.518us 1 1 100.00
csrng_err 2.000s 27.848us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 4.000s 68.518us 1 1 100.00
csrng_err 2.000s 27.848us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 4.000s 68.518us 1 1 100.00
csrng_err 2.000s 27.848us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 4.000s 68.518us 1 1 100.00
csrng_err 2.000s 27.848us 1 1 100.00
csrng_sec_cm 16.000s 42.024us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 4.000s 68.518us 1 1 100.00
csrng_err 2.000s 27.848us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 2.000s 150.395us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:660) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*])
csrng_cmds 103292408736469778646383374496451599376405457411837524962429426614451748384280 130
UVM_INFO @ 383173628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started
csrng_stress_all_with_rand_reset 80816641239545360439336417976751393614868679470041236917798220147450970221448 111
UVM_INFO @ 150395455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---