Simulation Results: edn/edn0

 
16/04/2026 00:05:37 DVSim: v1.30.1 sha: b849398 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.14 %
  • code
  • 79.37 %
  • assert
  • 93.06 %
  • func
  • 76.98 %
  • line
  • 96.74 %
  • branch
  • 88.84 %
  • cond
  • 83.28 %
  • toggle
  • 79.59 %
  • FSM
  • 48.39 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.840s 41.513us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.060s 15.027us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.970s 21.647us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.620s 86.423us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.970s 51.770us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.130s 21.943us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.970s 21.647us 1 1 100.00
edn_csr_aliasing 0.970s 51.770us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.080s 62.930us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.080s 62.930us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.080s 62.930us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.850s 38.548us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.360s 87.944us 1 1 100.00
errs 1 1 100.00
edn_err 1.090s 24.442us 1 1 100.00
disable 2 2 100.00
edn_disable 0.930s 25.801us 1 1 100.00
edn_disable_auto_req_mode 1.100s 26.985us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.710s 322.731us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.890s 13.223us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.780s 125.990us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.980s 886.681us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.980s 886.681us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.060s 15.027us 1 1 100.00
edn_csr_rw 0.970s 21.647us 1 1 100.00
edn_csr_aliasing 0.970s 51.770us 1 1 100.00
edn_same_csr_outstanding 1.060s 44.552us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.060s 15.027us 1 1 100.00
edn_csr_rw 0.970s 21.647us 1 1 100.00
edn_csr_aliasing 0.970s 51.770us 1 1 100.00
edn_same_csr_outstanding 1.060s 44.552us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 6.180s 994.658us 1 1 100.00
edn_tl_intg_err 2.050s 93.242us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.180s 20.650us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.360s 87.944us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.180s 994.658us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.180s 994.658us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 6.180s 994.658us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 6.180s 994.658us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.360s 87.944us 1 1 100.00
edn_sec_cm 6.180s 994.658us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.360s 87.944us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.050s 93.242us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
edn_stress_all_with_rand_reset 20.800s 1271.634us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
edn_stress_all_with_rand_reset 29722673534666526892684736501420386499536414082188808025101386374533174243433 169
UVM_INFO @ 1271633547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---