Simulation Results: edn/edn1

 
16/04/2026 00:05:37 DVSim: v1.30.1 sha: b849398 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.95 %
  • code
  • 82.82 %
  • assert
  • 97.14 %
  • func
  • 80.88 %
  • line
  • 97.72 %
  • branch
  • 92.42 %
  • cond
  • 89.62 %
  • toggle
  • 95.70 %
  • FSM
  • 38.64 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.940s 24.489us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.860s 32.895us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.770s 55.030us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.530s 181.811us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.030s 38.401us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.180s 119.962us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.770s 55.030us 1 1 100.00
edn_csr_aliasing 1.030s 38.401us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 0.870s 51.206us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 0.870s 51.206us 1 1 100.00
genbits 1 1 100.00
edn_genbits 0.870s 51.206us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.850s 32.448us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.420s 30.826us 1 1 100.00
errs 1 1 100.00
edn_err 1.020s 18.632us 1 1 100.00
disable 2 2 100.00
edn_disable 0.840s 12.322us 1 1 100.00
edn_disable_auto_req_mode 0.850s 48.987us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.450s 212.249us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.830s 17.067us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.760s 51.030us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.780s 113.349us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.780s 113.349us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.860s 32.895us 1 1 100.00
edn_csr_rw 0.770s 55.030us 1 1 100.00
edn_csr_aliasing 1.030s 38.401us 1 1 100.00
edn_same_csr_outstanding 1.240s 78.286us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.860s 32.895us 1 1 100.00
edn_csr_rw 0.770s 55.030us 1 1 100.00
edn_csr_aliasing 1.030s 38.401us 1 1 100.00
edn_same_csr_outstanding 1.240s 78.286us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 4.360s 4198.246us 1 1 100.00
edn_tl_intg_err 1.800s 530.429us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.850s 34.288us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.420s 30.826us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.360s 4198.246us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.360s 4198.246us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 4.360s 4198.246us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 4.360s 4198.246us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.420s 30.826us 1 1 100.00
edn_sec_cm 4.360s 4198.246us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.420s 30.826us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.800s 530.429us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 50.560s 14324.919us 1 1 100.00