Simulation Results: flash_ctrl

 
16/04/2026 00:05:37 DVSim: v1.30.1 sha: b849398 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.54 %
  • code
  • 94.09 %
  • assert
  • 96.76 %
  • func
  • 95.76 %
  • line
  • 95.96 %
  • branch
  • 97.14 %
  • cond
  • 93.22 %
  • toggle
  • 97.76 %
  • FSM
  • 86.39 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 24.040s 39.811us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 11.190s 17.012us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 12.820s 23.163us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 7.410s 34.287us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 33.710s 10880.516us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 32.920s 1725.987us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 9.230s 130.131us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 7.410s 34.287us 1 1 100.00
flash_ctrl_csr_aliasing 32.920s 1725.987us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 7.260s 51.573us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 5.830s 27.165us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 11.570s 69.698us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 15.100s 75.554us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1180.010s 96775.760us 1 1 100.00
flash_ctrl_hw_rma_reset 571.070s 160147.409us 1 1 100.00
flash_ctrl_lcmgr_intg 7.640s 22.406us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1087.480s 290428.888us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 265.230s 5618.457us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 7.560s 21.052us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 2031.340s 602850.411us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 72.740s 1411.262us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 13.510s 165.959us 1 1 100.00
flash_ctrl_rw_evict_all_en 12.550s 29.390us 1 1 100.00
flash_ctrl_re_evict 15.990s 66.585us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 119.610s 369.018us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 119.610s 369.018us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 296.790s 12605.826us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 11.500s 560.804us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 482.920s 1092.431us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 497.880s 4274.127us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 293.620s 1947.864us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 842.200s 801.025us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 5.840s 23.173us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 135.500s 1492.258us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 9.550s 29.398us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 5.790s 17.290us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 39.750s 164.774us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 34.370s 1768.697us 1 1 100.00
flash_ctrl_otp_reset 40.030s 75.760us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1180.010s 96775.760us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 139.480s 2941.159us 1 1 100.00
flash_ctrl_intr_wr 68.520s 11741.732us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 163.600s 70807.735us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 167.130s 85469.038us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 45.190s 4837.874us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 47.690s 649.347us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 11.560s 47.951us 1 1 100.00
flash_ctrl_ro_derr 113.230s 2547.221us 1 1 100.00
flash_ctrl_rw_derr 162.160s 2113.737us 1 1 100.00
flash_ctrl_derr_detect 127.850s 978.161us 1 1 100.00
flash_ctrl_integrity 468.570s 10392.541us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 12.590s 62.196us 1 1 100.00
flash_ctrl_ro_serr 91.950s 1375.593us 1 1 100.00
flash_ctrl_rw_serr 164.550s 3880.983us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 37.550s 581.107us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 68.720s 3795.808us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 102.830s 1813.418us 1 1 100.00
flash_ctrl_write_word_sweep 7.060s 40.338us 1 1 100.00
flash_ctrl_read_word_sweep 6.410s 25.591us 1 1 100.00
flash_ctrl_ro 74.910s 635.304us 1 1 100.00
flash_ctrl_rw 367.950s 14534.940us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 26.940s 2136.502us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 612.600s 40558.945us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 77.410s 10019.921us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 5.830s 184.738us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 5.510s 31.153us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 7.940s 35.266us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 7.940s 35.266us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 12.820s 23.163us 1 1 100.00
flash_ctrl_csr_rw 7.410s 34.287us 1 1 100.00
flash_ctrl_csr_aliasing 32.920s 1725.987us 1 1 100.00
flash_ctrl_same_csr_outstanding 8.770s 69.183us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 12.820s 23.163us 1 1 100.00
flash_ctrl_csr_rw 7.410s 34.287us 1 1 100.00
flash_ctrl_csr_aliasing 32.920s 1725.987us 1 1 100.00
flash_ctrl_same_csr_outstanding 8.770s 69.183us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 41.230s 55.646us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 41.230s 55.646us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 41.230s 55.646us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 41.230s 55.646us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 32.450s 248.656us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_sec_cm 1487.910s 4774.263us 1 1 100.00
flash_ctrl_tl_intg_err 138.100s 1387.735us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 138.100s 1387.735us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 138.100s 1387.735us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 17.430s 246.190us 1 1 100.00
flash_ctrl_wr_intg 6.470s 196.475us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 24.040s 39.811us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 40.030s 75.760us 1 1 100.00
flash_ctrl_disable 9.550s 29.398us 1 1 100.00
flash_ctrl_sec_info_access 52.240s 2210.282us 1 1 100.00
flash_ctrl_connect 5.790s 17.290us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 6.150s 27.769us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 7.410s 34.287us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 41.230s 55.646us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 7.410s 34.287us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 41.230s 55.646us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 7.410s 34.287us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 41.230s 55.646us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 9.550s 29.398us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 17.430s 246.190us 1 1 100.00
flash_ctrl_access_after_disable 6.790s 75.608us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 16.580s 93.522us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 9.550s 29.398us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 11.500s 560.804us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 367.950s 14534.940us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 164.550s 3880.983us 1 1 100.00
flash_ctrl_rw_derr 162.160s 2113.737us 1 1 100.00
flash_ctrl_integrity 468.570s 10392.541us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1180.010s 96775.760us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1487.910s 4774.263us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1487.910s 4774.263us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1487.910s 4774.263us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1487.910s 4774.263us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 9.010s 678.145us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 9.140s 164.431us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 7.500s 73.344us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1487.910s 4774.263us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1487.910s 4774.263us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1487.910s 4774.263us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 20.480s 254.400us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 189.570s 746.503us 1 1 100.00