Simulation Results: hmac

 
16/04/2026 00:05:37 DVSim: v1.30.1 sha: b849398 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.63 %
  • code
  • 97.68 %
  • assert
  • 96.70 %
  • func
  • 44.50 %
  • line
  • 99.64 %
  • branch
  • 98.84 %
  • cond
  • 95.78 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 8.910s 1226.505us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.870s 62.796us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.820s 50.451us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 7.480s 1708.185us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 6.440s 832.105us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.290s 117.420us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.820s 50.451us 1 1 100.00
hmac_csr_aliasing 6.440s 832.105us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 13.190s 1318.187us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 61.100s 1383.780us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 9.360s 175.325us 1 1 100.00
hmac_test_sha384_vectors 21.240s 1019.430us 1 1 100.00
hmac_test_sha512_vectors 23.240s 1142.532us 1 1 100.00
hmac_test_hmac256_vectors 8.550s 1055.529us 1 1 100.00
hmac_test_hmac384_vectors 8.570s 1008.818us 1 1 100.00
hmac_test_hmac512_vectors 9.090s 294.411us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 7.550s 1389.484us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 184.310s 2523.927us 1 1 100.00
error 1 1 100.00
hmac_error 108.060s 8319.137us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 71.090s 19481.600us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 8.910s 1226.505us 1 1 100.00
hmac_long_msg 13.190s 1318.187us 1 1 100.00
hmac_back_pressure 61.100s 1383.780us 1 1 100.00
hmac_datapath_stress 184.310s 2523.927us 1 1 100.00
hmac_burst_wr 7.550s 1389.484us 1 1 100.00
hmac_stress_all 140.170s 21692.514us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 8.910s 1226.505us 1 1 100.00
hmac_long_msg 13.190s 1318.187us 1 1 100.00
hmac_back_pressure 61.100s 1383.780us 1 1 100.00
hmac_datapath_stress 184.310s 2523.927us 1 1 100.00
hmac_wipe_secret 71.090s 19481.600us 1 1 100.00
hmac_test_sha256_vectors 9.360s 175.325us 1 1 100.00
hmac_test_sha384_vectors 21.240s 1019.430us 1 1 100.00
hmac_test_sha512_vectors 23.240s 1142.532us 1 1 100.00
hmac_test_hmac256_vectors 8.550s 1055.529us 1 1 100.00
hmac_test_hmac384_vectors 8.570s 1008.818us 1 1 100.00
hmac_test_hmac512_vectors 9.090s 294.411us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 8.910s 1226.505us 1 1 100.00
hmac_long_msg 13.190s 1318.187us 1 1 100.00
hmac_back_pressure 61.100s 1383.780us 1 1 100.00
hmac_datapath_stress 184.310s 2523.927us 1 1 100.00
hmac_burst_wr 7.550s 1389.484us 1 1 100.00
hmac_error 108.060s 8319.137us 1 1 100.00
hmac_wipe_secret 71.090s 19481.600us 1 1 100.00
hmac_test_sha256_vectors 9.360s 175.325us 1 1 100.00
hmac_test_sha384_vectors 21.240s 1019.430us 1 1 100.00
hmac_test_sha512_vectors 23.240s 1142.532us 1 1 100.00
hmac_test_hmac256_vectors 8.550s 1055.529us 1 1 100.00
hmac_test_hmac384_vectors 8.570s 1008.818us 1 1 100.00
hmac_test_hmac512_vectors 9.090s 294.411us 1 1 100.00
hmac_stress_all 140.170s 21692.514us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 140.170s 21692.514us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.590s 48.863us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.780s 21.789us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.000s 134.541us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.000s 134.541us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.870s 62.796us 1 1 100.00
hmac_csr_rw 0.820s 50.451us 1 1 100.00
hmac_csr_aliasing 6.440s 832.105us 1 1 100.00
hmac_same_csr_outstanding 1.350s 23.772us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.870s 62.796us 1 1 100.00
hmac_csr_rw 0.820s 50.451us 1 1 100.00
hmac_csr_aliasing 6.440s 832.105us 1 1 100.00
hmac_same_csr_outstanding 1.350s 23.772us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.020s 42.416us 1 1 100.00
hmac_tl_intg_err 3.570s 3296.912us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 3.570s 3296.912us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 8.910s 1226.505us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 4.580s 109.505us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 58.290s 4552.207us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.000s 98.410us 1 1 100.00