Simulation Results: i2c

 
16/04/2026 00:05:37 DVSim: v1.30.1 sha: b849398 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.02 %
  • code
  • 82.76 %
  • assert
  • 96.19 %
  • func
  • 85.10 %
  • line
  • 96.75 %
  • branch
  • 93.12 %
  • cond
  • 88.46 %
  • toggle
  • 89.66 %
  • FSM
  • 45.83 %
Validation stages
V1
100.00%
V2
97.56%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 15.120s 4811.558us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 37.550s 1614.991us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 0.830s 55.086us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 0.790s 42.482us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 2.440s 981.277us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 1.190s 207.769us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 1.060s 29.667us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 0.790s 42.482us 1 1 100.00
i2c_csr_aliasing 1.190s 207.769us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 1 1 100.00
i2c_host_error_intr 1.080s 63.220us 1 1 100.00
host_stress_all 1 1 100.00
i2c_host_stress_all 1014.380s 21243.398us 1 1 100.00
host_maxperf 1 1 100.00
i2c_host_perf 13.050s 8236.477us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 1.030s 19.732us 1 1 100.00
host_fifo_watermark 1 1 100.00
i2c_host_fifo_watermark 124.670s 13174.138us 1 1 100.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 36.660s 3637.919us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 1.140s 249.286us 1 1 100.00
i2c_host_fifo_fmt_empty 6.730s 564.715us 1 1 100.00
i2c_host_fifo_reset_rx 6.980s 297.939us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 101.440s 2605.875us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 18.920s 1036.571us 1 1 100.00
i2c_host_mode_toggle 1 1 100.00
i2c_host_mode_toggle 1.050s 142.099us 1 1 100.00
target_glitch 0 1 0.00
i2c_target_glitch 2.330s 476.154us 0 1 0.00
target_stress_all 1 1 100.00
i2c_target_stress_all 45.680s 40404.801us 1 1 100.00
target_maxperf 1 1 100.00
i2c_target_perf 4.060s 798.427us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 21.490s 1594.315us 1 1 100.00
i2c_target_intr_smoke 4.490s 4275.218us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 1.330s 305.457us 1 1 100.00
i2c_target_fifo_reset_tx 1.680s 253.159us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 86.100s 53159.010us 1 1 100.00
i2c_target_stress_rd 21.490s 1594.315us 1 1 100.00
i2c_target_intr_stress_wr 63.010s 18455.434us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 5.240s 4962.857us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 13.590s 3728.650us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 3.410s 3613.105us 1 1 100.00
target_mode_glitch 1 1 100.00
i2c_target_hrst 1.490s 205.686us 1 1 100.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 2.140s 3237.253us 1 1 100.00
i2c_target_fifo_watermarks_tx 0.990s 190.207us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 13.050s 8236.477us 1 1 100.00
i2c_host_perf_precise 1.670s 317.980us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 18.920s 1036.571us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 4.560s 264.973us 1 1 100.00
target_mode_nack_generation 3 3 100.00
i2c_target_nack_acqfull 2.120s 530.687us 1 1 100.00
i2c_target_nack_acqfull_addr 2.130s 620.061us 1 1 100.00
i2c_target_nack_txstretch 1.690s 130.241us 1 1 100.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 20.470s 1265.119us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 2.290s 1985.470us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 0.820s 40.641us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 0.860s 22.822us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 2.120s 485.775us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 2.120s 485.775us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 0.830s 55.086us 1 1 100.00
i2c_csr_rw 0.790s 42.482us 1 1 100.00
i2c_csr_aliasing 1.190s 207.769us 1 1 100.00
i2c_same_csr_outstanding 1.100s 32.131us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 0.830s 55.086us 1 1 100.00
i2c_csr_rw 0.790s 42.482us 1 1 100.00
i2c_csr_aliasing 1.190s 207.769us 1 1 100.00
i2c_same_csr_outstanding 1.100s 32.131us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_tl_intg_err 2.090s 1122.500us 1 1 100.00
i2c_sec_cm 0.970s 337.763us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 2.090s 1122.500us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 20.770s 518.999us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 3.300s 1868.877us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 10.880s 2579.526us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
i2c_target_glitch 10999950317035382323300048630591786729774635148187446092228989266144145923770 84
UVM_INFO @ 476154128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
i2c_target_unexp_stop 36062926997218867783949758474766855568370418268858702180207411065041087338104 79
UVM_ERROR @ 1868876938 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 1868876938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
i2c_host_stress_all_with_rand_reset 7832141204190736538397505353539561033495401742416676697184341601973654985199 97
UVM_INFO @ 518998960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 18211486246535498945839024747969343920085145929353429681871847067240734767515 86
UVM_INFO @ 2579525618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---