Simulation Results: kmac/unmasked

 
16/04/2026 00:05:37 DVSim: v1.30.1 sha: b849398 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.24 %
  • code
  • 89.32 %
  • assert
  • 97.90 %
  • func
  • 92.50 %
  • line
  • 97.39 %
  • branch
  • 95.11 %
  • cond
  • 91.35 %
  • toggle
  • 99.92 %
  • FSM
  • 62.81 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 8.280s 820.740us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.100s 79.644us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 1.400s 83.343us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 7.180s 2873.756us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 4.880s 766.648us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 2.280s 153.004us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 1.400s 83.343us 1 1 100.00
kmac_csr_aliasing 4.880s 766.648us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.920s 89.682us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.700s 148.328us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 2011.160s 25960.473us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 447.680s 62601.293us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 1670.640s 247786.985us 1 1 100.00
kmac_test_vectors_sha3_256 34.920s 9865.086us 1 1 100.00
kmac_test_vectors_sha3_384 821.870s 53152.236us 1 1 100.00
kmac_test_vectors_sha3_512 574.430s 18244.661us 1 1 100.00
kmac_test_vectors_shake_128 148.650s 20536.346us 1 1 100.00
kmac_test_vectors_shake_256 1131.470s 65338.639us 1 1 100.00
kmac_test_vectors_kmac 1.740s 78.984us 1 1 100.00
kmac_test_vectors_kmac_xof 2.450s 440.632us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 192.280s 173197.281us 1 1 100.00
app 1 1 100.00
kmac_app 6.530s 519.333us 1 1 100.00
app_with_partial_data 1 1 100.00
kmac_app_with_partial_data 132.560s 8781.352us 1 1 100.00
entropy_refresh 1 1 100.00
kmac_entropy_refresh 117.080s 8831.180us 1 1 100.00
error 1 1 100.00
kmac_error 202.760s 9898.941us 1 1 100.00
key_error 1 1 100.00
kmac_key_error 6.970s 2982.809us 1 1 100.00
sideload_invalid 1 1 100.00
kmac_sideload_invalid 1.900s 49.028us 1 1 100.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 18.730s 4084.288us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 25.430s 1744.072us 1 1 100.00
entropy_ready_error 1 1 100.00
kmac_entropy_ready_error 5.710s 3564.271us 1 1 100.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.170s 134.298us 1 1 100.00
stress_all 1 1 100.00
kmac_stress_all 1509.320s 114730.719us 1 1 100.00
intr_test 1 1 100.00
kmac_intr_test 0.880s 16.621us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 0.980s 26.589us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 2.400s 98.015us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 2.400s 98.015us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 1.100s 79.644us 1 1 100.00
kmac_csr_rw 1.400s 83.343us 1 1 100.00
kmac_csr_aliasing 4.880s 766.648us 1 1 100.00
kmac_same_csr_outstanding 1.720s 61.862us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 1.100s 79.644us 1 1 100.00
kmac_csr_rw 1.400s 83.343us 1 1 100.00
kmac_csr_aliasing 4.880s 766.648us 1 1 100.00
kmac_same_csr_outstanding 1.720s 61.862us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 2.050s 41.733us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 2.050s 41.733us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 2.050s 41.733us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 2.050s 41.733us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 5.480s 287.964us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_sec_cm 21.500s 11921.427us 1 1 100.00
kmac_tl_intg_err 4.610s 2146.910us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 4.610s 2146.910us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.170s 134.298us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 8.280s 820.740us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 192.280s 173197.281us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 2.050s 41.733us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 21.500s 11921.427us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 21.500s 11921.427us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 21.500s 11921.427us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 8.280s 820.740us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.170s 134.298us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 21.500s 11921.427us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 1 1 100.00
kmac_mubi 183.880s 9832.775us 1 1 100.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 8.280s 820.740us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
kmac_stress_all_with_rand_reset 24.890s 1695.569us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
kmac_stress_all_with_rand_reset 37165263715365773041606117800650056984947007053267772887581825809056861369086 124
UVM_INFO @ 1695569467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---