Simulation Results: lc_ctrl/volatile_unlock_disabled

 
16/04/2026 00:05:37 DVSim: v1.30.1 sha: b849398 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.34 %
  • code
  • 84.00 %
  • assert
  • 94.13 %
  • func
  • 92.88 %
  • line
  • 97.21 %
  • branch
  • 93.82 %
  • cond
  • 79.45 %
  • toggle
  • 87.86 %
  • FSM
  • 61.68 %
Validation stages
V1
100.00%
V2
96.67%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.220s 33.178us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.850s 62.345us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.790s 152.569us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.100s 67.393us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.050s 69.071us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.520s 53.438us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.790s 152.569us 1 1 100.00
lc_ctrl_csr_aliasing 1.050s 69.071us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 5.900s 139.010us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 10.980s 255.099us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.970s 12.241us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.810s 88.248us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.140s 550.796us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.100s 377.726us 1 1 100.00
security_escalation 6 7 85.71
lc_ctrl_state_failure 7.140s 550.796us 1 1 100.00
lc_ctrl_prog_failure 1.810s 88.248us 1 1 100.00
lc_ctrl_errors 5.100s 377.726us 1 1 100.00
lc_ctrl_security_escalation 5.620s 881.048us 1 1 100.00
lc_ctrl_jtag_state_failure 32.790s 24926.963us 1 1 100.00
lc_ctrl_jtag_prog_failure 9.460s 2090.507us 1 1 100.00
lc_ctrl_jtag_errors 1.590s 444.616us 0 1 0.00
jtag_access 12 13 92.31
lc_ctrl_jtag_smoke 7.910s 3787.727us 1 1 100.00
lc_ctrl_jtag_state_post_trans 13.410s 3360.890us 1 1 100.00
lc_ctrl_jtag_prog_failure 9.460s 2090.507us 1 1 100.00
lc_ctrl_jtag_errors 1.590s 444.616us 0 1 0.00
lc_ctrl_jtag_access 5.390s 1086.402us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 11.320s 3442.908us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.930s 74.555us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.140s 109.710us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 7.850s 405.972us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 7.500s 5521.153us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.050s 17.280us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.770s 105.783us 1 1 100.00
lc_ctrl_jtag_alert_test 1.130s 44.156us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 7.000s 2359.121us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.900s 26.750us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 162.850s 12681.059us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.300s 21.225us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.610s 53.193us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.610s 53.193us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.850s 62.345us 1 1 100.00
lc_ctrl_csr_rw 0.790s 152.569us 1 1 100.00
lc_ctrl_csr_aliasing 1.050s 69.071us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.460s 22.753us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.850s 62.345us 1 1 100.00
lc_ctrl_csr_rw 0.790s 152.569us 1 1 100.00
lc_ctrl_csr_aliasing 1.050s 69.071us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.460s 22.753us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.150s 132.482us 1 1 100.00
lc_ctrl_tl_intg_err 1.920s 111.885us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.920s 111.885us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 10.980s 255.099us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.140s 550.796us 1 1 100.00
lc_ctrl_sec_cm 6.150s 132.482us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.140s 550.796us 1 1 100.00
lc_ctrl_sec_cm 6.150s 132.482us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.140s 550.796us 1 1 100.00
lc_ctrl_sec_cm 6.150s 132.482us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.140s 550.796us 1 1 100.00
lc_ctrl_sec_cm 6.150s 132.482us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.140s 550.796us 1 1 100.00
lc_ctrl_sec_cm 6.150s 132.482us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.140s 550.796us 1 1 100.00
lc_ctrl_sec_cm 6.150s 132.482us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.140s 550.796us 1 1 100.00
lc_ctrl_sec_cm 6.150s 132.482us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.140s 550.796us 1 1 100.00
lc_ctrl_sec_cm 6.150s 132.482us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.620s 881.048us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 5.900s 139.010us 1 1 100.00
lc_ctrl_jtag_state_post_trans 13.410s 3360.890us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.080s 4994.549us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.080s 4994.549us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 6.670s 1838.597us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.240s 287.949us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.240s 287.949us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 108.230s 24128.371us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*])
lc_ctrl_jtag_errors 55243290999659343828518762758073889179668445731344065717102305538319779005651 194
UVM_INFO @ 444616490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---