Simulation Results: lc_ctrl/volatile_unlock_enabled

 
16/04/2026 00:05:37 DVSim: v1.30.1 sha: b849398 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.14 %
  • code
  • 83.04 %
  • assert
  • 94.13 %
  • func
  • 93.24 %
  • line
  • 96.97 %
  • branch
  • 93.32 %
  • cond
  • 78.59 %
  • toggle
  • 84.65 %
  • FSM
  • 61.68 %
Validation stages
V1
100.00%
V2
96.67%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.870s 24.156us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.090s 141.806us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.830s 26.462us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.270s 156.848us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.180s 19.776us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.930s 50.817us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.830s 26.462us 1 1 100.00
lc_ctrl_csr_aliasing 1.180s 19.776us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.170s 149.989us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 7.830s 2443.719us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.910s 35.813us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.520s 46.068us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.990s 1451.064us 1 1 100.00
lc_errors 0 1 0.00
lc_ctrl_errors 5.750s 233.855us 0 1 0.00
security_escalation 6 7 85.71
lc_ctrl_state_failure 7.990s 1451.064us 1 1 100.00
lc_ctrl_prog_failure 1.520s 46.068us 1 1 100.00
lc_ctrl_errors 5.750s 233.855us 0 1 0.00
lc_ctrl_security_escalation 6.140s 1825.562us 1 1 100.00
lc_ctrl_jtag_state_failure 15.740s 1467.082us 1 1 100.00
lc_ctrl_jtag_prog_failure 1.630s 64.190us 1 1 100.00
lc_ctrl_jtag_errors 18.220s 12882.290us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 1.590s 261.597us 1 1 100.00
lc_ctrl_jtag_state_post_trans 10.950s 6113.633us 1 1 100.00
lc_ctrl_jtag_prog_failure 1.630s 64.190us 1 1 100.00
lc_ctrl_jtag_errors 18.220s 12882.290us 1 1 100.00
lc_ctrl_jtag_access 5.100s 549.683us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 9.190s 3439.599us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.630s 532.762us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.480s 984.103us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 10.850s 673.823us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 15.300s 1538.703us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.090s 29.647us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.710s 481.084us 1 1 100.00
lc_ctrl_jtag_alert_test 1.440s 252.157us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 2.340s 207.939us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.400s 95.340us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 120.020s 8087.328us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.890s 15.370us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.130s 50.378us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.130s 50.378us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.090s 141.806us 1 1 100.00
lc_ctrl_csr_rw 0.830s 26.462us 1 1 100.00
lc_ctrl_csr_aliasing 1.180s 19.776us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.140s 56.838us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.090s 141.806us 1 1 100.00
lc_ctrl_csr_rw 0.830s 26.462us 1 1 100.00
lc_ctrl_csr_aliasing 1.180s 19.776us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.140s 56.838us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 7.660s 948.509us 1 1 100.00
lc_ctrl_tl_intg_err 1.950s 62.672us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.950s 62.672us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 7.830s 2443.719us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.990s 1451.064us 1 1 100.00
lc_ctrl_sec_cm 7.660s 948.509us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.990s 1451.064us 1 1 100.00
lc_ctrl_sec_cm 7.660s 948.509us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.990s 1451.064us 1 1 100.00
lc_ctrl_sec_cm 7.660s 948.509us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.990s 1451.064us 1 1 100.00
lc_ctrl_sec_cm 7.660s 948.509us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.990s 1451.064us 1 1 100.00
lc_ctrl_sec_cm 7.660s 948.509us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.990s 1451.064us 1 1 100.00
lc_ctrl_sec_cm 7.660s 948.509us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.990s 1451.064us 1 1 100.00
lc_ctrl_sec_cm 7.660s 948.509us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.990s 1451.064us 1 1 100.00
lc_ctrl_sec_cm 7.660s 948.509us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.140s 1825.562us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.170s 149.989us 1 1 100.00
lc_ctrl_jtag_state_post_trans 10.950s 6113.633us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.850s 1356.531us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.850s 1356.531us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 6.170s 414.350us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.890s 297.051us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.890s 297.051us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 1.550s 431.645us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*])
lc_ctrl_errors 98617138130243504561190952690840053305163405786545350134483282800537516947907 3628
UVM_INFO @ 233855009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 75995997994068846647778352764508664593803604328532608749800714988698764763670 150
UVM_INFO @ 431645335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---