Simulation Results: otp_ctrl

 
16/04/2026 00:05:37 DVSim: v1.30.1 sha: b849398 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 77.58 %
  • code
  • 75.84 %
  • assert
  • 91.17 %
  • func
  • 65.72 %
  • line
  • 88.38 %
  • branch
  • 81.47 %
  • cond
  • 89.28 %
  • toggle
  • 77.34 %
  • FSM
  • 42.71 %
Validation stages
V1
88.89%
V2
85.00%
V2S
66.67%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.450s 102.556us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 6.740s 294.961us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 1.700s 151.487us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.810s 49.205us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 2.920s 166.354us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 2.810s 118.468us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
otp_ctrl_csr_mem_rw_with_rand_reset 1.640s 65.079us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.810s 49.205us 1 1 100.00
otp_ctrl_csr_aliasing 2.810s 118.468us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.340s 123.704us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.990s 475.007us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 12.570s 329.785us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 3.000s 489.988us 1 1 100.00
partition_check 1 2 50.00
otp_ctrl_background_chks 16.770s 885.806us 1 1 100.00
otp_ctrl_check_fail 2.450s 196.420us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 4.810s 142.310us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 9.180s 1154.194us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 10.710s 1522.045us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 4.950s 373.726us 1 1 100.00
otp_ctrl_parallel_lc_esc 4.130s 209.143us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 16.320s 5961.325us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 4.150s 174.691us 0 1 0.00
test_access 1 1 100.00
otp_ctrl_test_access 4.980s 593.168us 1 1 100.00
stress_all 0 1 0.00
otp_ctrl_stress_all 42.660s 11272.858us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.380s 42.287us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.690s 105.979us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 2.520s 212.735us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 2.520s 212.735us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.700s 151.487us 1 1 100.00
otp_ctrl_csr_rw 1.810s 49.205us 1 1 100.00
otp_ctrl_csr_aliasing 2.810s 118.468us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.270s 857.794us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.700s 151.487us 1 1 100.00
otp_ctrl_csr_rw 1.810s 49.205us 1 1 100.00
otp_ctrl_csr_aliasing 2.810s 118.468us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.270s 857.794us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 0 1 0.00
otp_ctrl_sec_cm 172.930s 93542.433us 0 1 0.00
tl_intg_err 1 2 50.00
otp_ctrl_sec_cm 172.930s 93542.433us 0 1 0.00
otp_ctrl_tl_intg_err 7.290s 671.466us 1 1 100.00
prim_count_check 0 1 0.00
otp_ctrl_sec_cm 172.930s 93542.433us 0 1 0.00
prim_fsm_check 0 1 0.00
otp_ctrl_sec_cm 172.930s 93542.433us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 7.290s 671.466us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 6.740s 294.961us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 6.740s 294.961us 1 1 100.00
sec_cm_dai_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 172.930s 93542.433us 0 1 0.00
sec_cm_kdi_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 172.930s 93542.433us 0 1 0.00
sec_cm_lci_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 172.930s 93542.433us 0 1 0.00
sec_cm_part_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 172.930s 93542.433us 0 1 0.00
sec_cm_scrmbl_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 172.930s 93542.433us 0 1 0.00
sec_cm_timer_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 172.930s 93542.433us 0 1 0.00
sec_cm_dai_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 172.930s 93542.433us 0 1 0.00
sec_cm_kdi_seed_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 172.930s 93542.433us 0 1 0.00
sec_cm_kdi_entropy_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 172.930s 93542.433us 0 1 0.00
sec_cm_lci_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 172.930s 93542.433us 0 1 0.00
sec_cm_part_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 172.930s 93542.433us 0 1 0.00
sec_cm_scrmbl_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 172.930s 93542.433us 0 1 0.00
sec_cm_timer_integ_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 172.930s 93542.433us 0 1 0.00
sec_cm_timer_cnsty_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 172.930s 93542.433us 0 1 0.00
sec_cm_timer_lfsr_redun 0 1 0.00
otp_ctrl_sec_cm 172.930s 93542.433us 0 1 0.00
sec_cm_dai_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 4.130s 209.143us 1 1 100.00
otp_ctrl_sec_cm 172.930s 93542.433us 0 1 0.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.130s 209.143us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.130s 209.143us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 4.130s 209.143us 1 1 100.00
otp_ctrl_macro_errs 4.150s 174.691us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.130s 209.143us 1 1 100.00
sec_cm_timer_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 4.130s 209.143us 1 1 100.00
otp_ctrl_sec_cm 172.930s 93542.433us 0 1 0.00
sec_cm_dai_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 4.130s 209.143us 1 1 100.00
otp_ctrl_sec_cm 172.930s 93542.433us 0 1 0.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.130s 209.143us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.130s 209.143us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 4.130s 209.143us 1 1 100.00
otp_ctrl_macro_errs 4.150s 174.691us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.130s 209.143us 1 1 100.00
sec_cm_timer_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 4.130s 209.143us 1 1 100.00
otp_ctrl_sec_cm 172.930s 93542.433us 0 1 0.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 3.000s 489.988us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 2.450s 196.420us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 9.180s 1154.194us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 9.180s 1154.194us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 9.180s 1154.194us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 9.180s 1154.194us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 9.180s 1154.194us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 6.740s 294.961us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 9.180s 1154.194us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 6.740s 294.961us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 172.930s 93542.433us 0 1 0.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 4.810s 142.310us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 6.740s 294.961us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 6.740s 294.961us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 4.150s 174.691us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 11.830s 5875.371us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 1.150s 48.353us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_*
otp_ctrl_check_fail 56481734596284824763522858688195095231313592311117230307585530553504259592602 1015
UVM_INFO @ 196419613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 46206452582320815763842250182165796033772076608069714245717620765174973962770 2252
UVM_INFO @ 174691162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 91396981969369263338330249226582509426437332162989302483210567695660704805005 19449
UVM_INFO @ 11272857551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = *
otp_ctrl_stress_all_with_rand_reset 94120693222542142555129956010711135914674411887465626737833110091314566560000 93
UVM_INFO @ 48352595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_csr_mem_rw_with_rand_reset 11172815147862838393668796144572807951022637008326217240911667142877875493388 98
UVM_INFO @ 65078985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [otp_ctrl_common_vseq] expect alert:fatal_check_error to fire
otp_ctrl_sec_cm 70771506470685021876854205870066258076825042630307212338058566737258027373441 1542
UVM_INFO @ 93542433452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---