Simulation Results: pattgen

 
16/04/2026 00:05:37 DVSim: v1.30.1 sha: b849398 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.37 %
  • code
  • 98.87 %
  • assert
  • 94.82 %
  • func
  • 89.42 %
  • block
  • 100.00 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • toggle
  • 96.61 %
Validation stages
V1
100.00%
V2
81.82%
V2S
100.00%
V3
0.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pattgen_smoke 3.000s 595.789us 1 1 100.00
csr_hw_reset 1 1 100.00
pattgen_csr_hw_reset 2.000s 16.539us 1 1 100.00
csr_rw 1 1 100.00
pattgen_csr_rw 1.000s 13.960us 1 1 100.00
csr_bit_bash 1 1 100.00
pattgen_csr_bit_bash 2.000s 136.543us 1 1 100.00
csr_aliasing 1 1 100.00
pattgen_csr_aliasing 2.000s 99.097us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pattgen_csr_mem_rw_with_rand_reset 1.000s 93.712us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pattgen_csr_rw 1.000s 13.960us 1 1 100.00
pattgen_csr_aliasing 2.000s 99.097us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
perf 0 1 0.00
pattgen_perf 769.000s 600000.000us 0 1 0.00
cnt_rollover 1 1 100.00
cnt_rollover 1.000s 113.645us 1 1 100.00
error 1 1 100.00
pattgen_error 2.000s 42.438us 1 1 100.00
stress_all 0 1 0.00
pattgen_stress_all 0.000s 0.000us 0 1 0.00
alert_test 1 1 100.00
pattgen_alert_test 1.000s 30.195us 1 1 100.00
intr_test 1 1 100.00
pattgen_intr_test 1.000s 39.087us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pattgen_tl_errors 1.000s 92.315us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pattgen_tl_errors 1.000s 92.315us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pattgen_csr_hw_reset 2.000s 16.539us 1 1 100.00
pattgen_csr_rw 1.000s 13.960us 1 1 100.00
pattgen_csr_aliasing 2.000s 99.097us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 54.507us 1 1 100.00
tl_d_partial_access 4 4 100.00
pattgen_csr_hw_reset 2.000s 16.539us 1 1 100.00
pattgen_csr_rw 1.000s 13.960us 1 1 100.00
pattgen_csr_aliasing 2.000s 99.097us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 54.507us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pattgen_tl_intg_err 1.000s 148.776us 1 1 100.00
pattgen_sec_cm 1.000s 64.296us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pattgen_tl_intg_err 1.000s 148.776us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
pattgen_stress_all_with_rand_reset 38.000s 5470.154us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
pattgen_inactive_level 191.000s 10137.631us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
pattgen_perf 11764737236078662602371704045773745289364917647423530584825732055944061256711 99
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=25)
pattgen_inactive_level 46841964103061299141140979920963891336892440812055580551907404006059145862872 99
UVM_INFO @ 10137630709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
pattgen_stress_all_with_rand_reset 43475277766697181749559659146941845365028585303850785735869568259370865211344 204
UVM_ERROR @ 1013707245 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1013707245 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 3/10
UVM_INFO @ 1013790581 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Job killed!
pattgen_stress_all 51590898783478662925704375897481488473710225848761615560340793270554171313106 None