Simulation Results: pwrmgr

 
16/04/2026 00:05:37 DVSim: v1.30.1 sha: b849398 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.43 %
  • code
  • 94.41 %
  • assert
  • 96.34 %
  • func
  • 95.55 %
  • line
  • 98.92 %
  • branch
  • 95.61 %
  • cond
  • 93.49 %
  • toggle
  • 90.02 %
  • FSM
  • 94.00 %
Validation stages
V1
100.00%
V2
86.67%
V2S
80.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.670s 29.432us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.630s 44.256us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.800s 62.076us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.640s 349.792us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.880s 50.102us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.890s 39.215us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.800s 62.076us 1 1 100.00
pwrmgr_csr_aliasing 0.880s 50.102us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 1.070s 237.352us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 1.070s 237.352us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.840s 95.487us 1 1 100.00
pwrmgr_lowpower_invalid 0.760s 165.454us 1 1 100.00
reset 1 2 50.00
pwrmgr_reset 1.730s 1000.000us 0 1 0.00
pwrmgr_reset_invalid 0.930s 101.292us 1 1 100.00
main_power_glitch_reset 0 1 0.00
pwrmgr_reset 1.730s 1000.000us 0 1 0.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.800s 95.802us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.690s 56.691us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.690s 33.017us 1 1 100.00
stress_all 0 1 0.00
pwrmgr_stress_all 8.540s 10289.648us 0 1 0.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.710s 32.582us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.150s 110.690us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.150s 110.690us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.630s 44.256us 1 1 100.00
pwrmgr_csr_rw 0.800s 62.076us 1 1 100.00
pwrmgr_csr_aliasing 0.880s 50.102us 1 1 100.00
pwrmgr_same_csr_outstanding 0.750s 20.628us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.630s 44.256us 1 1 100.00
pwrmgr_csr_rw 0.800s 62.076us 1 1 100.00
pwrmgr_csr_aliasing 0.880s 50.102us 1 1 100.00
pwrmgr_same_csr_outstanding 0.750s 20.628us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
pwrmgr_tl_intg_err 0.620s 12.419us 0 1 0.00
pwrmgr_sec_cm 0.900s 6.966us 0 1 0.00
prim_count_check 0 1 0.00
pwrmgr_sec_cm 0.900s 6.966us 0 1 0.00
prim_fsm_check 0 1 0.00
pwrmgr_sec_cm 0.900s 6.966us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
pwrmgr_tl_intg_err 0.620s 12.419us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 2.110s 800.744us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 1 1 100.00
pwrmgr_wakeup_reset 0.800s 95.802us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.830s 48.823us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.660s 33.105us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 0 1 0.00
pwrmgr_sec_cm 0.900s 6.966us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
pwrmgr_sec_cm 0.900s 6.966us 0 1 0.00
sec_cm_fsm_terminal 0 1 0.00
pwrmgr_sec_cm 0.900s 6.966us 0 1 0.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.620s 60.921us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.670s 42.527us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.820s 146.433us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.800s 62.076us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.800s 62.076us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 0 1 0.00
pwrmgr_escalation_timeout 0.890s 103.098us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 5.970s 2372.414us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
pwrmgr_reset 9818196103615365367585309046485790386836308232675849122825121868998509589046 78
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((!clk_en) || status)'
pwrmgr_escalation_timeout 66245231289304271969658560250999986969780337103877660583976212252864364678358 79
UVM_ERROR @ 103098236 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 103098236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [pwrmgr_common_vseq] expect alert:fatal_fault to fire
pwrmgr_tl_intg_err 42709143575558559033436164736766959372567850221725624791096820590292335846696 82
UVM_INFO @ 12419027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_sec_cm 37946992350182261090590683979666671475973122981471643259959619946816526449117 78
UVM_INFO @ 6965618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_vseq.sv:62) [pwrmgr_reset_vseq] wait timeout occurred!
pwrmgr_stress_all 104474959112204959792272151207092511620160592062531843702650252417174900887002 221
UVM_INFO @ 10289648122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---