Simulation Results: rom_ctrl/32kb

 
16/04/2026 00:05:37 DVSim: v1.30.1 sha: b849398 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.92 %
  • code
  • 99.36 %
  • assert
  • 96.80 %
  • func
  • 97.61 %
  • line
  • 99.59 %
  • branch
  • 99.27 %
  • cond
  • 97.92 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.650s 318.792us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 7.310s 184.561us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 4.720s 218.698us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.810s 922.428us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 4.220s 285.144us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 5.600s 177.961us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 4.720s 218.698us 1 1 100.00
rom_ctrl_csr_aliasing 4.220s 285.144us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.580s 300.227us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 4.100s 175.582us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 4.740s 411.884us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 12.530s 473.223us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 6.660s 228.886us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.460s 129.006us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 5.810s 201.410us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 5.810s 201.410us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 7.310s 184.561us 1 1 100.00
rom_ctrl_csr_rw 4.720s 218.698us 1 1 100.00
rom_ctrl_csr_aliasing 4.220s 285.144us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.350s 213.515us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 7.310s 184.561us 1 1 100.00
rom_ctrl_csr_rw 4.720s 218.698us 1 1 100.00
rom_ctrl_csr_aliasing 4.220s 285.144us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.350s 213.515us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 55.770s 1655.568us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 16.560s 2278.728us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 203.130s 920.261us 1 1 100.00
rom_ctrl_tl_intg_err 42.410s 1346.215us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 203.130s 920.261us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 203.130s 920.261us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 55.770s 1655.568us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 55.770s 1655.568us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 55.770s 1655.568us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 55.770s 1655.568us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 55.770s 1655.568us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 203.130s 920.261us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 203.130s 920.261us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.650s 318.792us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.650s 318.792us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.650s 318.792us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 42.410s 1346.215us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 55.770s 1655.568us 1 1 100.00
rom_ctrl_kmac_err_chk 6.660s 228.886us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 55.770s 1655.568us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 55.770s 1655.568us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 55.770s 1655.568us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 16.560s 2278.728us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 203.130s 920.261us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 266.170s 6360.781us 1 1 100.00