Simulation Results: rv_timer

 
16/04/2026 00:05:37 DVSim: v1.30.1 sha: b849398 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.68 %
  • code
  • 100.00 %
  • assert
  • 96.50 %
  • func
  • 93.53 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 1.370s 481.023us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.570s 20.746us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.580s 46.237us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.350s 1065.429us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.720s 23.346us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.710s 21.637us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.580s 46.237us 1 1 100.00
rv_timer_csr_aliasing 0.720s 23.346us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.770s 2135.358us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 1.040s 1614.042us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 9.210s 22579.592us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 9.210s 22579.592us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 8.220s 7234.496us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.580s 34.560us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.570s 45.113us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.330s 80.077us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.330s 80.077us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.570s 20.746us 1 1 100.00
rv_timer_csr_rw 0.580s 46.237us 1 1 100.00
rv_timer_csr_aliasing 0.720s 23.346us 1 1 100.00
rv_timer_same_csr_outstanding 0.930s 31.870us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.570s 20.746us 1 1 100.00
rv_timer_csr_rw 0.580s 46.237us 1 1 100.00
rv_timer_csr_aliasing 0.720s 23.346us 1 1 100.00
rv_timer_same_csr_outstanding 0.930s 31.870us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.710s 54.015us 1 1 100.00
rv_timer_tl_intg_err 1.090s 292.706us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.090s 292.706us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.720s 61.448us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.580s 188.541us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 32.720s 4979.752us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == *
rv_timer_min 12955716030366016363872759486065364569664811709976997683769525272922215885774 75
UVM_INFO @ 61448165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 833662841769698591913890224844743173369181602308402104432040193474162473847 75
UVM_INFO @ 2135358388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*])
rv_timer_max 22921932487724621109215939982570614529499623686447391975085729446830633592621 75
UVM_INFO @ 188541422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---