| V1 |
|
100.00% |
| V2 |
|
92.31% |
| V2S |
|
100.00% |
| unmapped |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| spi_device_flash_and_tpm | 28.960s | 3386.536us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| spi_device_csr_hw_reset | 1.330s | 22.937us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| spi_device_csr_rw | 2.410s | 134.653us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| spi_device_csr_bit_bash | 9.210s | 795.505us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| spi_device_csr_aliasing | 17.520s | 1261.978us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| spi_device_csr_mem_rw_with_rand_reset | 2.720s | 268.955us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| spi_device_csr_rw | 2.410s | 134.653us | 1 | 1 | 100.00 | |
| spi_device_csr_aliasing | 17.520s | 1261.978us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| spi_device_mem_walk | 0.780s | 75.117us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| spi_device_mem_partial_access | 1.490s | 220.060us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| csb_read | 1 | 1 | 100.00 | |||
| spi_device_csb_read | 0.800s | 31.337us | 1 | 1 | 100.00 | |
| mem_parity | 0 | 1 | 0.00 | |||
| spi_device_mem_parity | 0.770s | 1.646us | 0 | 1 | 0.00 | |
| mem_cfg | 0 | 1 | 0.00 | |||
| spi_device_ram_cfg | 0.670s | 5.168us | 0 | 1 | 0.00 | |
| tpm_read | 1 | 1 | 100.00 | |||
| spi_device_tpm_rw | 1.400s | 36.206us | 1 | 1 | 100.00 | |
| tpm_write | 1 | 1 | 100.00 | |||
| spi_device_tpm_rw | 1.400s | 36.206us | 1 | 1 | 100.00 | |
| tpm_hw_reg | 2 | 2 | 100.00 | |||
| spi_device_tpm_read_hw_reg | 4.390s | 1414.660us | 1 | 1 | 100.00 | |
| spi_device_tpm_sts_read | 0.740s | 55.971us | 1 | 1 | 100.00 | |
| tpm_fully_random_case | 1 | 1 | 100.00 | |||
| spi_device_tpm_all | 6.560s | 1013.632us | 1 | 1 | 100.00 | |
| pass_cmd_filtering | 2 | 2 | 100.00 | |||
| spi_device_pass_cmd_filtering | 5.380s | 4242.899us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 15.230s | 1661.654us | 1 | 1 | 100.00 | |
| pass_addr_translation | 2 | 2 | 100.00 | |||
| spi_device_pass_addr_payload_swap | 6.100s | 1949.996us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 15.230s | 1661.654us | 1 | 1 | 100.00 | |
| pass_payload_translation | 2 | 2 | 100.00 | |||
| spi_device_pass_addr_payload_swap | 6.100s | 1949.996us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 15.230s | 1661.654us | 1 | 1 | 100.00 | |
| cmd_info_slots | 1 | 1 | 100.00 | |||
| spi_device_flash_all | 15.230s | 1661.654us | 1 | 1 | 100.00 | |
| cmd_read_status | 2 | 2 | 100.00 | |||
| spi_device_intercept | 6.690s | 3249.076us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 15.230s | 1661.654us | 1 | 1 | 100.00 | |
| cmd_read_jedec | 2 | 2 | 100.00 | |||
| spi_device_intercept | 6.690s | 3249.076us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 15.230s | 1661.654us | 1 | 1 | 100.00 | |
| cmd_read_sfdp | 2 | 2 | 100.00 | |||
| spi_device_intercept | 6.690s | 3249.076us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 15.230s | 1661.654us | 1 | 1 | 100.00 | |
| cmd_fast_read | 2 | 2 | 100.00 | |||
| spi_device_intercept | 6.690s | 3249.076us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 15.230s | 1661.654us | 1 | 1 | 100.00 | |
| cmd_read_pipeline | 2 | 2 | 100.00 | |||
| spi_device_intercept | 6.690s | 3249.076us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 15.230s | 1661.654us | 1 | 1 | 100.00 | |
| flash_cmd_upload | 1 | 1 | 100.00 | |||
| spi_device_upload | 6.840s | 2731.904us | 1 | 1 | 100.00 | |
| mailbox_command | 1 | 1 | 100.00 | |||
| spi_device_mailbox | 5.060s | 297.483us | 1 | 1 | 100.00 | |
| mailbox_cross_outside_command | 1 | 1 | 100.00 | |||
| spi_device_mailbox | 5.060s | 297.483us | 1 | 1 | 100.00 | |
| mailbox_cross_inside_command | 1 | 1 | 100.00 | |||
| spi_device_mailbox | 5.060s | 297.483us | 1 | 1 | 100.00 | |
| cmd_read_buffer | 2 | 2 | 100.00 | |||
| spi_device_flash_mode | 13.820s | 1149.896us | 1 | 1 | 100.00 | |
| spi_device_read_buffer_direct | 4.850s | 950.264us | 1 | 1 | 100.00 | |
| cmd_dummy_cycle | 2 | 2 | 100.00 | |||
| spi_device_mailbox | 5.060s | 297.483us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 15.230s | 1661.654us | 1 | 1 | 100.00 | |
| quad_spi | 1 | 1 | 100.00 | |||
| spi_device_flash_all | 15.230s | 1661.654us | 1 | 1 | 100.00 | |
| dual_spi | 1 | 1 | 100.00 | |||
| spi_device_flash_all | 15.230s | 1661.654us | 1 | 1 | 100.00 | |
| 4b_3b_feature | 1 | 1 | 100.00 | |||
| spi_device_cfg_cmd | 3.850s | 1783.376us | 1 | 1 | 100.00 | |
| write_enable_disable | 1 | 1 | 100.00 | |||
| spi_device_cfg_cmd | 3.850s | 1783.376us | 1 | 1 | 100.00 | |
| TPM_with_flash_or_passthrough_mode | 1 | 1 | 100.00 | |||
| spi_device_flash_and_tpm | 28.960s | 3386.536us | 1 | 1 | 100.00 | |
| tpm_and_flash_trans_with_min_inactive_time | 1 | 1 | 100.00 | |||
| spi_device_flash_and_tpm_min_idle | 40.410s | 9307.013us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| spi_device_stress_all | 135.760s | 34091.574us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| spi_device_alert_test | 0.660s | 14.092us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| spi_device_intr_test | 0.710s | 27.037us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| spi_device_tl_errors | 3.740s | 158.038us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| spi_device_tl_errors | 3.740s | 158.038us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| spi_device_csr_hw_reset | 1.330s | 22.937us | 1 | 1 | 100.00 | |
| spi_device_csr_rw | 2.410s | 134.653us | 1 | 1 | 100.00 | |
| spi_device_csr_aliasing | 17.520s | 1261.978us | 1 | 1 | 100.00 | |
| spi_device_same_csr_outstanding | 1.590s | 49.019us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| spi_device_csr_hw_reset | 1.330s | 22.937us | 1 | 1 | 100.00 | |
| spi_device_csr_rw | 2.410s | 134.653us | 1 | 1 | 100.00 | |
| spi_device_csr_aliasing | 17.520s | 1261.978us | 1 | 1 | 100.00 | |
| spi_device_same_csr_outstanding | 1.590s | 49.019us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| spi_device_sec_cm | 1.580s | 94.782us | 1 | 1 | 100.00 | |
| spi_device_tl_intg_err | 16.610s | 2968.612us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| spi_device_tl_intg_err | 16.610s | 2968.612us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 1 | 1 | 100.00 | |||
| spi_device_flash_mode_ignore_cmds | 70.670s | 57719.518us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) | ||||
| spi_device_mem_parity | 19226731235178803929627121580218138545282836897741361364305737744031885118063 | 76 |
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 1013304 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 1013304 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[905])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
|
|
| UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) | ||||
| spi_device_ram_cfg | 69206765495772049647466656099304050863904455710905499797512088009668760734783 | 76 |
UVM_ERROR @ 2734650 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x503130 [10100000011000100110000] vs 0x0 [0])
UVM_ERROR @ 2789650 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc993d8 [110010011001001111011000] vs 0x0 [0])
UVM_ERROR @ 2794650 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x52be58 [10100101011111001011000] vs 0x0 [0])
UVM_ERROR @ 2824650 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x360587 [1101100000010110000111] vs 0x0 [0])
|
|