Simulation Results: spi_device/2p

 
16/04/2026 00:05:37 DVSim: v1.30.1 sha: b849398 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 80.97 %
  • code
  • 94.17 %
  • assert
  • 87.48 %
  • func
  • 61.26 %
  • line
  • 99.09 %
  • branch
  • 98.30 %
  • cond
  • 96.34 %
  • toggle
  • 87.74 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 36.410s 5953.057us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.170s 87.091us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.870s 328.965us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 26.930s 1808.220us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 9.690s 1642.782us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.080s 84.949us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.870s 328.965us 1 1 100.00
spi_device_csr_aliasing 9.690s 1642.782us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.940s 75.942us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.570s 474.544us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.790s 55.427us 1 1 100.00
mem_parity 1 1 100.00
spi_device_mem_parity 0.960s 28.442us 1 1 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 0.790s 16.831us 1 1 100.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.260s 133.674us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.260s 133.674us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 2.940s 1672.542us 1 1 100.00
spi_device_tpm_sts_read 1.080s 41.594us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 0.680s 23.794us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 2.000s 120.345us 1 1 100.00
spi_device_flash_all 32.250s 28081.462us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 7.400s 10014.944us 1 1 100.00
spi_device_flash_all 32.250s 28081.462us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 7.400s 10014.944us 1 1 100.00
spi_device_flash_all 32.250s 28081.462us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 32.250s 28081.462us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 6.700s 1038.715us 1 1 100.00
spi_device_flash_all 32.250s 28081.462us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 6.700s 1038.715us 1 1 100.00
spi_device_flash_all 32.250s 28081.462us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 6.700s 1038.715us 1 1 100.00
spi_device_flash_all 32.250s 28081.462us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 6.700s 1038.715us 1 1 100.00
spi_device_flash_all 32.250s 28081.462us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 6.700s 1038.715us 1 1 100.00
spi_device_flash_all 32.250s 28081.462us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 4.420s 320.686us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 11.110s 1202.279us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 11.110s 1202.279us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 11.110s 1202.279us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 2.490s 132.151us 1 1 100.00
spi_device_read_buffer_direct 11.410s 1456.428us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 11.110s 1202.279us 1 1 100.00
spi_device_flash_all 32.250s 28081.462us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 32.250s 28081.462us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 32.250s 28081.462us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 8.210s 1151.030us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 8.210s 1151.030us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 36.410s 5953.057us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 194.360s 32918.850us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 8.120s 2351.793us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.810s 16.201us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.840s 106.841us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 3.000s 55.006us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 3.000s 55.006us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.170s 87.091us 1 1 100.00
spi_device_csr_rw 1.870s 328.965us 1 1 100.00
spi_device_csr_aliasing 9.690s 1642.782us 1 1 100.00
spi_device_same_csr_outstanding 3.090s 163.323us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.170s 87.091us 1 1 100.00
spi_device_csr_rw 1.870s 328.965us 1 1 100.00
spi_device_csr_aliasing 9.690s 1642.782us 1 1 100.00
spi_device_same_csr_outstanding 3.090s 163.323us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.130s 57.427us 1 1 100.00
spi_device_tl_intg_err 10.760s 3067.152us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 10.760s 3067.152us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 38.260s 10850.097us 1 1 100.00