Simulation Results: spi_host

 
16/04/2026 00:05:37 DVSim: v1.30.1 sha: b849398 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.47 %
  • code
  • 95.03 %
  • assert
  • 94.13 %
  • func
  • 88.24 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 7.000s 458.252us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 34.597us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 43.828us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 982.473us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 40.965us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 1.000s 49.656us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 43.828us 1 1 100.00
spi_host_csr_aliasing 1.000s 40.965us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 17.959us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 2.000s 27.163us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 1.000s 19.760us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 2.000s 221.074us 1 1 100.00
spi_host_error_cmd 1.000s 33.808us 1 1 100.00
spi_host_event 9.000s 3903.914us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 1.000s 36.527us 1 1 100.00
speed 1 1 100.00
spi_host_speed 1.000s 36.527us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 1.000s 36.527us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 5.000s 159.160us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 34.123us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 1.000s 36.527us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 1.000s 36.527us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 7.000s 458.252us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 7.000s 458.252us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 3.000s 196.359us 1 1 100.00
spien 1 1 100.00
spi_host_spien 13.000s 2123.211us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 47.000s 17734.534us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 2.000s 143.041us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 2.000s 221.074us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 18.477us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 16.349us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 103.909us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 103.909us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 34.597us 1 1 100.00
spi_host_csr_rw 1.000s 43.828us 1 1 100.00
spi_host_csr_aliasing 1.000s 40.965us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 23.337us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 34.597us 1 1 100.00
spi_host_csr_rw 1.000s 43.828us 1 1 100.00
spi_host_csr_aliasing 1.000s 40.965us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 23.337us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 2.000s 402.043us 1 1 100.00
spi_host_sec_cm 1.000s 164.959us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 402.043us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_host_upper_range_clkdiv 74.000s 4697.923us 1 1 100.00