Simulation Results: sram_ctrl/main

 
16/04/2026 00:05:37 DVSim: v1.30.1 sha: b849398 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.88 %
  • code
  • 96.79 %
  • assert
  • 96.46 %
  • func
  • 94.40 %
  • block
  • 96.07 %
  • line
  • 96.39 %
  • branch
  • 94.68 %
  • toggle
  • 96.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
90.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 8.000s 3098.299us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 31.022us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 2.000s 12.311us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.000s 27.431us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 121.921us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 365.304us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 2.000s 12.311us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 121.921us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 190.000s 5254.622us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 43.000s 1434.919us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 16.000s 12685.882us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 128.000s 18444.514us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 271.000s 32816.602us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 53.000s 12391.805us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 22.000s 13528.577us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 25.000s 21979.100us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 6.000s 1344.402us 1 1 100.00
sram_ctrl_partial_access_b2b 161.000s 11539.835us 1 1 100.00
max_throughput 1 3 33.33
sram_ctrl_max_throughput 5.000s 685.055us 0 1 0.00
sram_ctrl_throughput_w_partial_write 5.000s 1341.506us 1 1 100.00
sram_ctrl_throughput_w_readback 6.000s 685.399us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 14.000s 980.177us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.000s 670.731us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 634.000s 57525.556us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 26.918us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 25.008us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 25.008us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 31.022us 1 1 100.00
sram_ctrl_csr_rw 2.000s 12.311us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 121.921us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 36.992us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 31.022us 1 1 100.00
sram_ctrl_csr_rw 2.000s 12.311us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 121.921us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 36.992us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 23.000s 14697.446us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 5.000s 764.082us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 382.047us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 5.000s 764.082us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 382.047us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 14.000s 980.177us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 14.000s 980.177us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 2.000s 12.311us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 25.000s 21979.100us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 25.000s 21979.100us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 25.000s 21979.100us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 22.000s 13528.577us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.000s 675.301us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 23.000s 14697.446us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 4.000s 1492.081us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 8.000s 3098.299us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 8.000s 3098.299us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 25.000s 21979.100us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 5.000s 764.082us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 22.000s 13528.577us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 5.000s 764.082us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 5.000s 764.082us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 8.000s 3098.299us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 5.000s 764.082us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 20.000s 2022.763us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (sram_ctrl_base_vseq.sv:329) [sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-*:*], *'b0}) <= *; mask dist {'* :/ * - partial_access_pct, [* : '* - *] :/ partial_access_pct};}) Randomization failed!
sram_ctrl_max_throughput 111200416850855951305666466465158788808486299435329327891944476232352277125737 102
UVM_INFO @ 685054790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 77016572211780456601382099777388271087519085955286259713361176794567399566545 102
UVM_INFO @ 685398556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---