Simulation Results: sram_ctrl/ret

 
16/04/2026 00:05:37 DVSim: v1.30.1 sha: b849398 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.55 %
  • code
  • 83.85 %
  • assert
  • 96.43 %
  • func
  • 94.37 %
  • block
  • 94.37 %
  • line
  • 95.28 %
  • branch
  • 91.17 %
  • toggle
  • 82.28 %
  • FSM
  • 66.67 %
Validation stages
V1
87.50%
V2
90.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 88.309us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 29.959us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 29.597us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 100.997us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 25.474us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.000s 104.368us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 29.597us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 25.474us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 5.000s 240.740us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 4.000s 229.098us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 9.000s 738.101us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 244.000s 6507.339us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 44.000s 3077.586us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 20.000s 7516.147us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 4.000s 416.739us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 7.000s 1899.785us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 304.287us 1 1 100.00
sram_ctrl_partial_access_b2b 194.000s 14138.363us 1 1 100.00
max_throughput 1 3 33.33
sram_ctrl_max_throughput 2.000s 38.645us 0 1 0.00
sram_ctrl_throughput_w_partial_write 1.000s 34.535us 1 1 100.00
sram_ctrl_throughput_w_readback 2.000s 171.953us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 7.000s 171.291us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.000s 30.756us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 48.000s 4085.451us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 17.405us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 5.000s 861.930us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 5.000s 861.930us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 29.959us 1 1 100.00
sram_ctrl_csr_rw 1.000s 29.597us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 25.474us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 60.646us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 29.959us 1 1 100.00
sram_ctrl_csr_rw 1.000s 29.597us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 25.474us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 60.646us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 820.185us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 317.556us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 143.441us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 317.556us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 143.441us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 7.000s 171.291us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 7.000s 171.291us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 29.597us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 7.000s 1899.785us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 7.000s 1899.785us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 7.000s 1899.785us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 4.000s 416.739us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 1.000s 149.959us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 820.185us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 1.000s 75.289us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 88.309us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 88.309us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 7.000s 1899.785us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 317.556us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 4.000s 416.739us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 317.556us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 317.556us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 88.309us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 317.556us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 6.000s 477.079us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (sram_ctrl_base_vseq.sv:329) [sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-*:*], *'b0}) <= *; mask dist {'* :/ * - partial_access_pct, [* : '* - *] :/ partial_access_pct};}) Randomization failed!
sram_ctrl_max_throughput 101477291827156471742494888387255104992153963373070426231948655316276509667811 102
UVM_INFO @ 38645371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 27936793849641845796331850794418227948557765619865704942363306633985554319170 102
UVM_INFO @ 171953393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: *
sram_ctrl_csr_mem_rw_with_rand_reset 90831247498565348126300067969250625495751327171517049352601784146944823755281 88
UVM_INFO @ 104367671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---