Simulation Results: sysrst_ctrl

 
16/04/2026 00:05:37 DVSim: v1.30.1 sha: b849398 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.09 %
  • code
  • 89.88 %
  • assert
  • 88.60 %
  • func
  • 64.80 %
  • line
  • 95.33 %
  • branch
  • 96.11 %
  • cond
  • 93.21 %
  • toggle
  • 100.00 %
  • FSM
  • 64.74 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 4.550s 2112.420us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 2.680s 2473.917us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 4.400s 2399.555us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 2.470s 2320.558us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 12.530s 6023.982us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 2.190s 2139.273us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 43.290s 76210.067us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 7.600s 2593.537us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 5.030s 2047.085us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 2.190s 2139.273us 1 1 100.00
sysrst_ctrl_csr_aliasing 7.600s 2593.537us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 34.180s 57918.022us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 141.810s 69893.044us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 73.210s 158850.446us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 4.050s 3534.261us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 2.100s 2523.269us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 2.330s 2233.370us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 11.910s 5178.056us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 2.990s 2622.934us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 3.350s 7187.971us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 21.410s 36994.798us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 331.910s 336306.376us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 4.480s 2012.034us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 4.360s 2011.202us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 4.420s 2589.858us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 4.420s 2589.858us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 12.530s 6023.982us 1 1 100.00
sysrst_ctrl_csr_rw 2.190s 2139.273us 1 1 100.00
sysrst_ctrl_csr_aliasing 7.600s 2593.537us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 6.270s 9511.407us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 12.530s 6023.982us 1 1 100.00
sysrst_ctrl_csr_rw 2.190s 2139.273us 1 1 100.00
sysrst_ctrl_csr_aliasing 7.600s 2593.537us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 6.270s 9511.407us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 15.290s 42232.250us 1 1 100.00
sysrst_ctrl_tl_intg_err 10.520s 22461.086us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 10.520s 22461.086us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 11.310s 5427.000us 1 1 100.00