Simulation Results: uart

 
16/04/2026 00:05:37 DVSim: v1.30.1 sha: b849398 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.89 %
  • code
  • 95.84 %
  • assert
  • 97.12 %
  • func
  • 61.69 %
  • line
  • 99.17 %
  • branch
  • 97.44 %
  • cond
  • 95.22 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.430s 611.452us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.810s 14.366us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.850s 96.880us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.930s 702.335us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.990s 64.149us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.810s 296.699us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.850s 96.880us 1 1 100.00
uart_csr_aliasing 0.990s 64.149us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 26.310s 62459.108us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.430s 611.452us 1 1 100.00
uart_tx_rx 26.310s 62459.108us 1 1 100.00
parity_error 2 2 100.00
uart_intr 16.870s 18907.431us 1 1 100.00
uart_rx_parity_err 112.860s 124590.557us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 26.310s 62459.108us 1 1 100.00
uart_intr 16.870s 18907.431us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 60.930s 54666.024us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 17.650s 64325.638us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 30.190s 161210.093us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 16.870s 18907.431us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 16.870s 18907.431us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 16.870s 18907.431us 1 1 100.00
perf 1 1 100.00
uart_perf 154.170s 17489.571us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 2.790s 5529.623us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 2.790s 5529.623us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 15.280s 12222.351us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 6.840s 5381.249us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 10.350s 6783.846us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 12.990s 5384.295us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 507.310s 115303.413us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 435.590s 169805.114us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.860s 14.280us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.770s 23.146us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.710s 173.955us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.710s 173.955us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.810s 14.366us 1 1 100.00
uart_csr_rw 0.850s 96.880us 1 1 100.00
uart_csr_aliasing 0.990s 64.149us 1 1 100.00
uart_same_csr_outstanding 0.740s 19.932us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.810s 14.366us 1 1 100.00
uart_csr_rw 0.850s 96.880us 1 1 100.00
uart_csr_aliasing 0.990s 64.149us 1 1 100.00
uart_same_csr_outstanding 0.740s 19.932us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.250s 110.199us 1 1 100.00
uart_tl_intg_err 1.490s 93.407us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.490s 93.407us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
uart_stress_all_with_rand_reset 13.190s 14979.177us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: *
uart_noise_filter 83836286072931885159482291312826941634626373300086639884390675595029788109837 77
UVM_ERROR @ 4648222803 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 4648233220 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (98 [0x62] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 4675088246 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 4675088246 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = *
uart_stress_all_with_rand_reset 43479699334910294837289642644460541917566075301025568739972690228332499710847 142
UVM_ERROR @ 12800996867 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 12807087770 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 12807996860 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 12813724127 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0