Simulation Results: adc_ctrl

 
17/04/2026 01:26:32 DVSim: v1.31.0 sha: ee0af46 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 70.23 %
  • code
  • 96.28 %
  • assert
  • 95.95 %
  • func
  • 18.46 %
  • line
  • 99.02 %
  • branch
  • 97.71 %
  • cond
  • 92.76 %
  • toggle
  • 100.00 %
  • FSM
  • 91.89 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 1.740s 5974.710us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 0.990s 985.408us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.580s 537.341us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 15.590s 20134.282us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 4.110s 1170.752us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.220s 599.484us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.580s 537.341us 1 1 100.00
adc_ctrl_csr_aliasing 4.110s 1170.752us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 1 1 100.00
adc_ctrl_filters_polled 9.360s 17324.307us 1 1 100.00
filters_polled_fixed 1 1 100.00
adc_ctrl_filters_polled_fixed 56.460s 37764.645us 1 1 100.00
filters_interrupt 1 1 100.00
adc_ctrl_filters_interrupt 3.950s 18089.946us 1 1 100.00
filters_interrupt_fixed 1 1 100.00
adc_ctrl_filters_interrupt_fixed 23.000s 50204.156us 1 1 100.00
filters_wakeup 1 1 100.00
adc_ctrl_filters_wakeup 86.430s 50257.173us 1 1 100.00
filters_wakeup_fixed 1 1 100.00
adc_ctrl_filters_wakeup_fixed 47.520s 27157.128us 1 1 100.00
filters_both 1 1 100.00
adc_ctrl_filters_both 32.550s 19384.470us 1 1 100.00
clock_gating 1 1 100.00
adc_ctrl_clock_gating 1.120s 27561.905us 1 1 100.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 1.900s 3839.693us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 33.680s 28605.321us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 50.240s 116175.977us 1 1 100.00
stress_all 1 1 100.00
adc_ctrl_stress_all 35.440s 23253.591us 1 1 100.00
alert_test 1 1 100.00
adc_ctrl_alert_test 1.070s 312.553us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 0.840s 368.642us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 1.920s 583.916us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 1.920s 583.916us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 0.990s 985.408us 1 1 100.00
adc_ctrl_csr_rw 1.580s 537.341us 1 1 100.00
adc_ctrl_csr_aliasing 4.110s 1170.752us 1 1 100.00
adc_ctrl_same_csr_outstanding 3.350s 5266.876us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 0.990s 985.408us 1 1 100.00
adc_ctrl_csr_rw 1.580s 537.341us 1 1 100.00
adc_ctrl_csr_aliasing 4.110s 1170.752us 1 1 100.00
adc_ctrl_same_csr_outstanding 3.350s 5266.876us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 12.610s 7497.688us 1 1 100.00
adc_ctrl_tl_intg_err 3.210s 4521.364us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 3.210s 4521.364us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
adc_ctrl_stress_all_with_rand_reset 12.700s 63062.144us 1 1 100.00