Simulation Results: aes/masked

 
17/04/2026 01:26:32 DVSim: v1.31.0 sha: ee0af46 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.35 %
  • code
  • 96.13 %
  • assert
  • 98.29 %
  • func
  • 70.64 %
  • block
  • 96.49 %
  • line
  • 97.59 %
  • branch
  • 91.45 %
  • toggle
  • 98.05 %
  • FSM
  • 97.42 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 3.000s 66.182us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 276.381us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 60.819us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 65.384us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 3.000s 981.743us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 101.449us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 82.480us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 65.384us 1 1 100.00
aes_csr_aliasing 2.000s 101.449us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 276.381us 1 1 100.00
aes_config_error 2.000s 90.625us 1 1 100.00
aes_stress 3.000s 186.207us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 276.381us 1 1 100.00
aes_config_error 2.000s 90.625us 1 1 100.00
aes_stress 3.000s 186.207us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 186.207us 1 1 100.00
aes_b2b 19.000s 768.960us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 186.207us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 276.381us 1 1 100.00
aes_config_error 2.000s 90.625us 1 1 100.00
aes_stress 3.000s 186.207us 1 1 100.00
aes_alert_reset 5.000s 311.477us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 3.000s 112.525us 1 1 100.00
aes_config_error 2.000s 90.625us 1 1 100.00
aes_alert_reset 5.000s 311.477us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 104.293us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 8.000s 614.489us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 7.000s 271.410us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 5.000s 311.477us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 186.207us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 186.207us 1 1 100.00
aes_sideload 2.000s 63.154us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 4.000s 213.810us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 50.000s 2231.110us 1 1 100.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 3.000s 121.553us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 73.094us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 111.784us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 111.784us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 60.819us 1 1 100.00
aes_csr_rw 2.000s 65.384us 1 1 100.00
aes_csr_aliasing 2.000s 101.449us 1 1 100.00
aes_same_csr_outstanding 2.000s 253.886us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 60.819us 1 1 100.00
aes_csr_rw 2.000s 65.384us 1 1 100.00
aes_csr_aliasing 2.000s 101.449us 1 1 100.00
aes_same_csr_outstanding 2.000s 253.886us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 3.000s 68.710us 1 1 100.00
fault_inject 3 3 100.00
aes_fi 6.000s 637.644us 1 1 100.00
aes_control_fi 3.000s 212.139us 1 1 100.00
aes_cipher_fi 3.000s 61.678us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 86.591us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 86.591us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 86.591us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 86.591us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 695.362us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 6.000s 1320.527us 1 1 100.00
aes_tl_intg_err 3.000s 684.315us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 684.315us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 5.000s 311.477us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 86.591us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 86.591us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 276.381us 1 1 100.00
aes_stress 3.000s 186.207us 1 1 100.00
aes_alert_reset 5.000s 311.477us 1 1 100.00
aes_core_fi 3.000s 95.925us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 3.000s 121.553us 1 1 100.00
aes_config_error 2.000s 90.625us 1 1 100.00
aes_stress 3.000s 186.207us 1 1 100.00
aes_core_fi 3.000s 95.925us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 86.591us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 88.532us 1 1 100.00
aes_stress 3.000s 186.207us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 186.207us 1 1 100.00
aes_sideload 2.000s 63.154us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 88.532us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 88.532us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 88.532us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 88.532us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 88.532us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 186.207us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 186.207us 1 1 100.00
sec_cm_main_fsm_sparse 1 1 100.00
aes_fi 6.000s 637.644us 1 1 100.00
sec_cm_main_fsm_redun 4 4 100.00
aes_fi 6.000s 637.644us 1 1 100.00
aes_control_fi 3.000s 212.139us 1 1 100.00
aes_cipher_fi 3.000s 61.678us 1 1 100.00
aes_ctr_fi 2.000s 68.080us 1 1 100.00
sec_cm_cipher_fsm_sparse 1 1 100.00
aes_fi 6.000s 637.644us 1 1 100.00
sec_cm_cipher_fsm_redun 3 3 100.00
aes_fi 6.000s 637.644us 1 1 100.00
aes_control_fi 3.000s 212.139us 1 1 100.00
aes_cipher_fi 3.000s 61.678us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 3.000s 61.678us 1 1 100.00
sec_cm_ctr_fsm_sparse 1 1 100.00
aes_fi 6.000s 637.644us 1 1 100.00
sec_cm_ctr_fsm_redun 3 3 100.00
aes_fi 6.000s 637.644us 1 1 100.00
aes_control_fi 3.000s 212.139us 1 1 100.00
aes_ctr_fi 2.000s 68.080us 1 1 100.00
sec_cm_ghash_fsm_sparse 1 1 100.00
aes_fi 6.000s 637.644us 1 1 100.00
sec_cm_ctrl_sparse 4 4 100.00
aes_fi 6.000s 637.644us 1 1 100.00
aes_control_fi 3.000s 212.139us 1 1 100.00
aes_cipher_fi 3.000s 61.678us 1 1 100.00
aes_ctr_fi 2.000s 68.080us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 5.000s 311.477us 1 1 100.00
sec_cm_main_fsm_local_esc 4 4 100.00
aes_fi 6.000s 637.644us 1 1 100.00
aes_control_fi 3.000s 212.139us 1 1 100.00
aes_cipher_fi 3.000s 61.678us 1 1 100.00
aes_ctr_fi 2.000s 68.080us 1 1 100.00
sec_cm_cipher_fsm_local_esc 4 4 100.00
aes_fi 6.000s 637.644us 1 1 100.00
aes_control_fi 3.000s 212.139us 1 1 100.00
aes_cipher_fi 3.000s 61.678us 1 1 100.00
aes_ctr_fi 2.000s 68.080us 1 1 100.00
sec_cm_ctr_fsm_local_esc 3 3 100.00
aes_fi 6.000s 637.644us 1 1 100.00
aes_control_fi 3.000s 212.139us 1 1 100.00
aes_ctr_fi 2.000s 68.080us 1 1 100.00
sec_cm_ghash_fsm_local_esc 2 2 100.00
aes_fi 6.000s 637.644us 1 1 100.00
aes_ghash_fi 2.000s 72.176us 1 1 100.00
sec_cm_data_reg_local_esc 3 3 100.00
aes_fi 6.000s 637.644us 1 1 100.00
aes_control_fi 3.000s 212.139us 1 1 100.00
aes_cipher_fi 3.000s 61.678us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 15.000s 731.350us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
aes_stress_all_with_rand_reset 52276547075620241502607518766123902103629614837677508830030078914656648025792 831
UVM_INFO @ 731350342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---