Simulation Results: chip

 
17/04/2026 01:26:32 DVSim: v1.31.0 sha: ee0af46 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 75.95 %
  • code
  • 85.50 %
  • assert
  • 97.37 %
  • func
  • 44.98 %
  • line
  • 94.73 %
  • branch
  • 94.38 %
  • cond
  • 90.00 %
  • toggle
  • 91.23 %
  • FSM
  • 57.14 %
Validation stages
V1
100.00%
V2
78.06%
V2S
100.00%
V3
65.38%
unmapped
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 117.990s 2754.225us 1 1 100.00
chip_sw_example_rom 101.580s 2728.960us 1 1 100.00
chip_sw_example_manufacturer 156.550s 2549.170us 1 1 100.00
chip_sw_example_concurrency 143.990s 2662.616us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 339.650s 7736.765us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 270.530s 4429.311us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 163.310s 4323.333us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 5121.580s 37024.255us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
chip_csr_mem_rw_with_rand_reset 312.510s 6011.835us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 5121.580s 37024.255us 1 1 100.00
chip_csr_rw 270.530s 4429.311us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 7.540s 169.543us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 280.260s 3988.935us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 280.260s 3988.935us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 280.260s 3988.935us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 365.660s 4692.372us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 365.660s 4692.372us 1 1 100.00
chip_sw_uart_tx_rx_idx1 346.200s 4203.712us 1 1 100.00
chip_sw_uart_tx_rx_idx2 325.430s 4342.448us 1 1 100.00
chip_sw_uart_tx_rx_idx3 385.050s 4850.616us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 333.380s 4419.455us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 418.320s 4642.991us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 715.380s 9067.377us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 212.240s 4456.317us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 212.240s 4456.317us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 209.300s 3843.614us 1 1 100.00
chip_sw_sleep_pin_wake 0 1 0.00
chip_sw_sleep_pin_wake 152.070s 3333.384us 0 1 0.00
chip_sw_sleep_pin_retention 1 1 100.00
chip_sw_sleep_pin_retention 196.250s 3695.281us 1 1 100.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 129.260s 3297.810us 1 1 100.00
chip_tap_straps_testunlock0 115.320s 3524.672us 1 1 100.00
chip_tap_straps_rma 238.120s 4993.197us 1 1 100.00
chip_tap_straps_prod 109.040s 3115.574us 1 1 100.00
chip_sw_pattgen_ios 1 1 100.00
chip_sw_pattgen_ios 172.200s 2828.435us 1 1 100.00
chip_sw_sleep_pwm_pulses 1 1 100.00
chip_sw_sleep_pwm_pulses 726.820s 9257.530us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 382.390s 4995.140us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 382.390s 4995.140us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 619.070s 6960.383us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 1231.910s 13552.019us 0 1 0.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 375.910s 3906.162us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 602.000s 5993.403us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3731.770s 19458.560us 1 1 100.00
chip_sw_aes_enc_jitter_en 161.820s 2756.035us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 599.550s 6122.656us 1 1 100.00
chip_sw_hmac_enc_jitter_en 170.320s 2838.908us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1082.210s 9440.680us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 181.360s 3088.952us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 399.580s 4622.874us 1 1 100.00
chip_sw_clkmgr_jitter 118.310s 3077.858us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 240.160s 3818.599us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 2 2 100.00
chip_sw_sensor_ctrl_alert 559.910s 8811.339us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 217.780s 5082.583us 1 1 100.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 135.370s 2543.755us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 217.780s 5082.583us 1 1 100.00
chip_sw_smoketest 17 17 100.00
chip_sw_flash_scrambling_smoketest 133.510s 2489.439us 1 1 100.00
chip_sw_aes_smoketest 217.660s 2427.272us 1 1 100.00
chip_sw_aon_timer_smoketest 194.730s 3040.685us 1 1 100.00
chip_sw_clkmgr_smoketest 135.940s 2514.608us 1 1 100.00
chip_sw_csrng_smoketest 169.050s 2497.244us 1 1 100.00
chip_sw_entropy_src_smoketest 931.860s 7533.568us 1 1 100.00
chip_sw_gpio_smoketest 199.960s 2985.339us 1 1 100.00
chip_sw_hmac_smoketest 186.030s 3114.671us 1 1 100.00
chip_sw_kmac_smoketest 175.080s 2714.997us 1 1 100.00
chip_sw_otbn_smoketest 576.450s 5708.271us 1 1 100.00
chip_sw_pwrmgr_smoketest 199.590s 5407.616us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 256.640s 6709.114us 1 1 100.00
chip_sw_rv_plic_smoketest 138.860s 2510.415us 1 1 100.00
chip_sw_rv_timer_smoketest 222.760s 3156.483us 1 1 100.00
chip_sw_rstmgr_smoketest 161.380s 3204.656us 1 1 100.00
chip_sw_sram_ctrl_smoketest 168.740s 2783.893us 1 1 100.00
chip_sw_uart_smoketest 165.260s 2905.527us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 182.140s 3427.136us 1 1 100.00
chip_sw_rom_functests 0 1 0.00
rom_keymgr_functest 363.470s 5268.627us 0 1 0.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 8004.420s 62692.699us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 3104.440s 15060.474us 1 1 100.00
chip_sw_rom_raw_unlock 0 1 0.00
rom_raw_unlock 51.931s 0.000us 0 1 0.00
chip_sw_power_idle_load 0 1 0.00
chip_sw_power_idle_load 249.880s 3530.941us 0 1 0.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 193.290s 3647.613us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 7209.320s 55927.580us 1 1 100.00
chip_sw_inject_scramble_seed 1 1 100.00
chip_sw_inject_scramble_seed 7894.530s 59750.010us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 60.380s 2102.302us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 60.380s 2102.302us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 5121.580s 37024.255us 1 1 100.00
chip_same_csr_outstanding 2574.130s 29309.388us 1 1 100.00
chip_csr_hw_reset 339.650s 7736.765us 1 1 100.00
chip_csr_rw 270.530s 4429.311us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 5121.580s 37024.255us 1 1 100.00
chip_same_csr_outstanding 2574.130s 29309.388us 1 1 100.00
chip_csr_hw_reset 339.650s 7736.765us 1 1 100.00
chip_csr_rw 270.530s 4429.311us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 40.340s 1874.066us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 7.670s 55.721us 1 1 100.00
xbar_smoke_large_delays 61.200s 9147.138us 1 1 100.00
xbar_smoke_slow_rsp 46.420s 4752.957us 1 1 100.00
xbar_random_zero_delays 16.480s 245.187us 1 1 100.00
xbar_random_large_delays 117.370s 20158.392us 1 1 100.00
xbar_random_slow_rsp 142.370s 15641.522us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 35.920s 1255.622us 1 1 100.00
xbar_error_and_unmapped_addr 24.490s 927.884us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 53.100s 2548.774us 1 1 100.00
xbar_error_and_unmapped_addr 24.490s 927.884us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 46.230s 948.720us 1 1 100.00
xbar_access_same_device_slow_rsp 703.910s 77907.411us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 58.530s 2654.684us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 189.820s 7536.943us 1 1 100.00
xbar_stress_all_with_error 73.850s 1416.778us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 15.750s 69.914us 1 1 100.00
xbar_stress_all_with_reset_error 280.780s 9537.226us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 3104.440s 15060.474us 1 1 100.00
rom_e2e_shutdown_output 1 1 100.00
rom_e2e_shutdown_output 2498.850s 25359.090us 1 1 100.00
rom_e2e_shutdown_exception_c 1 1 100.00
rom_e2e_shutdown_exception_c 2797.940s 15587.294us 1 1 100.00
rom_e2e_boot_policy_valid 0 15 0.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 161.679s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 79.251s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 53.673s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 59.891s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 49.572s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 70.947s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 123.833s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 81.993s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 82.678s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 82.637s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 72.914s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 82.665s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 83.216s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 81.307s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 130.563s 0.000us 0 1 0.00
rom_e2e_sigverify_always 0 15 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 21.320s 10.360us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 18.210s 10.280us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 18.520s 10.100us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 18.180s 10.320us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 17.740s 10.100us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 15.740s 10.140us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 17.040s 10.100us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 18.830s 10.140us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 18.710s 10.160us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 16.750s 10.340us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 18.810s 10.140us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 16.680s 10.160us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 16.760s 10.400us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 16.440s 10.400us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 17.360s 10.180us 0 1 0.00
rom_e2e_asm_init 0 5 0.00
rom_e2e_asm_init_test_unlocked0 75.573s 0.000us 0 1 0.00
rom_e2e_asm_init_dev 28.759s 0.000us 0 1 0.00
rom_e2e_asm_init_prod 214.233s 0.000us 0 1 0.00
rom_e2e_asm_init_prod_end 27.677s 0.000us 0 1 0.00
rom_e2e_asm_init_rma 19.807s 0.000us 0 1 0.00
rom_e2e_keymgr_init 3 3 100.00
rom_e2e_keymgr_init_rom_ext_meas 5867.080s 29240.720us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_no_meas 5913.680s 28968.319us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 5951.020s 29455.756us 1 1 100.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 3055.430s 16202.671us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3126.270s 35414.702us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3126.270s 35414.702us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 150.130s 3411.255us 1 1 100.00
chip_sw_aes_enc_jitter_en 161.820s 2756.035us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 117.990s 2632.432us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 145.350s 2852.652us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_sideload_aes 654.420s 6377.087us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 137.250s 3267.563us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 348.490s 5339.436us 1 1 100.00
chip_sw_all_escalation_resets 1 1 100.00
chip_sw_all_escalation_resets 434.900s 6153.968us 1 1 100.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 531.390s 5414.866us 1 1 100.00
chip_plic_all_irqs_10 250.960s 3824.782us 1 1 100.00
chip_plic_all_irqs_20 414.500s 5112.564us 1 1 100.00
chip_sw_alert_handler_entropy 1 1 100.00
chip_sw_alert_handler_entropy 222.230s 3455.825us 1 1 100.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 1169.010s 15248.989us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 204.960s 4307.595us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 105.930s 2608.112us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0.000s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 892.310s 7197.356us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1088.570s 8373.291us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 818.800s 7761.962us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 8630.410s 256635.574us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 231.270s 3455.327us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 199.590s 5407.616us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 231.270s 3455.327us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 596.160s 8542.690us 1 1 100.00
chip_sw_aon_timer_sleep_wdog_bite_reset 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 596.160s 8542.690us 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 285.880s 7185.477us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 366.350s 5186.792us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 611.200s 5642.102us 1 1 100.00
chip_sw_aes_idle 145.350s 2852.652us 1 1 100.00
chip_sw_hmac_enc_idle 147.810s 3411.381us 1 1 100.00
chip_sw_kmac_idle 160.550s 2633.678us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 350.690s 5205.370us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 314.860s 4402.216us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 338.330s 5728.642us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 314.200s 4066.047us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 824.420s 11749.711us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 345.430s 4116.936us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 387.090s 4890.703us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 386.710s 4707.333us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 378.730s 5000.307us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 415.300s 4611.531us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 332.330s 4405.865us 1 1 100.00
chip_sw_ast_clk_outputs 619.070s 6960.383us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 718.200s 12968.857us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 386.710s 4707.333us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 378.730s 5000.307us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 375.910s 3906.162us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 602.000s 5993.403us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3731.770s 19458.560us 1 1 100.00
chip_sw_aes_enc_jitter_en 161.820s 2756.035us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 599.550s 6122.656us 1 1 100.00
chip_sw_hmac_enc_jitter_en 170.320s 2838.908us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1082.210s 9440.680us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 181.360s 3088.952us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 399.580s 4622.874us 1 1 100.00
chip_sw_clkmgr_jitter 118.310s 3077.858us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 155.160s 3118.016us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 412.690s 5291.039us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 594.120s 7525.679us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 4081.350s 25264.790us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 203.110s 3801.340us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 164.970s 3063.005us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 735.170s 9074.613us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 202.890s 3029.002us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 338.710s 5541.507us 1 1 100.00
chip_sw_flash_init_reduced_freq 1178.780s 22845.941us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 1135.560s 10662.958us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 619.070s 6960.383us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 1 1 100.00
chip_sw_clkmgr_sleep_frequency 382.460s 5224.864us 1 1 100.00
chip_sw_clkmgr_reset_frequency 1 1 100.00
chip_sw_clkmgr_reset_frequency 213.700s 3439.765us 1 1 100.00
chip_sw_clkmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 434.900s 6153.968us 1 1 100.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 892.310s 7197.356us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 1188.840s 8474.362us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 0 1 0.00
chip_sw_csrng_fuse_en_sw_app_read_test 210.660s 3110.267us 0 1 0.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 477.900s 6345.762us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 189.090s 2565.276us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 3964.780s 23688.552us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 171.780s 2829.691us 1 1 100.00
chip_sw_edn_entropy_reqs 905.600s 8457.028us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 171.780s 2829.691us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 1188.840s 8474.362us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 167.860s 3354.581us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 1211.860s 20434.741us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 587.450s 6336.524us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 602.000s 5993.403us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 414.790s 4466.965us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 375.910s 3906.162us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 3691.380s 42961.744us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 1211.860s 20434.741us 1 1 100.00
chip_sw_flash_idle_low_power 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 223.190s 3660.746us 1 1 100.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_key_derivation 1478.490s 12363.153us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 156.920s 3167.365us 0 1 0.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 3691.380s 42961.744us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 156.920s 3167.365us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 156.920s 3167.365us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_wr_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 156.920s 3167.365us 0 1 0.00
chip_sw_flash_lc_seed_hw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 156.920s 3167.365us 0 1 0.00
chip_sw_flash_lc_escalate_en 1 1 100.00
chip_sw_all_escalation_resets 434.900s 6153.968us 1 1 100.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 189.170s 9219.397us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 596.100s 6186.681us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 434.200s 6503.845us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 434.200s 6503.845us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 148.470s 2639.790us 1 1 100.00
chip_sw_hmac_enc_jitter_en 170.320s 2838.908us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 147.810s 3411.381us 1 1 100.00
chip_sw_hmac_all_configurations 1 1 100.00
chip_sw_hmac_oneshot 1272.750s 9936.718us 1 1 100.00
chip_sw_hmac_multistream_mode 1 1 100.00
chip_sw_hmac_multistream 724.990s 6397.955us 1 1 100.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 360.980s 4219.945us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 418.320s 4868.308us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 433.360s 5386.715us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 269.600s 3485.541us 1 1 100.00
chip_sw_keymgr_key_derivation 2 2 100.00
chip_sw_keymgr_key_derivation 1478.490s 12363.153us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1082.210s 9440.680us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1 1 100.00
chip_sw_keymgr_sideload_kmac 1727.470s 12751.925us 1 1 100.00
chip_sw_keymgr_sideload_aes 1 1 100.00
chip_sw_keymgr_sideload_aes 654.420s 6377.087us 1 1 100.00
chip_sw_keymgr_sideload_otbn 1 1 100.00
chip_sw_keymgr_sideload_otbn 2322.160s 12571.102us 1 1 100.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 154.920s 3079.516us 1 1 100.00
chip_sw_kmac_mode_kmac 181.570s 3348.494us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 181.360s 3088.952us 1 1 100.00
chip_sw_kmac_app_keymgr 1 1 100.00
chip_sw_keymgr_key_derivation 1478.490s 12363.153us 1 1 100.00
chip_sw_kmac_app_lc 1 1 100.00
chip_sw_lc_ctrl_transition 341.940s 6181.291us 1 1 100.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 146.700s 3096.985us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 1433.150s 10480.109us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 160.550s 2633.678us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 348.490s 5339.436us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 129.260s 3297.810us 1 1 100.00
chip_tap_straps_rma 238.120s 4993.197us 1 1 100.00
chip_tap_straps_prod 109.040s 3115.574us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 162.700s 2500.768us 1 1 100.00
chip_sw_lc_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 341.940s 6181.291us 1 1 100.00
chip_sw_lc_ctrl_transitions 1 1 100.00
chip_sw_lc_ctrl_transition 341.940s 6181.291us 1 1 100.00
chip_sw_lc_ctrl_kmac_req 1 1 100.00
chip_sw_lc_ctrl_transition 341.940s 6181.291us 1 1 100.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_key_derivation_prod 1771.530s 13573.907us 1 1 100.00
chip_sw_lc_ctrl_broadcast 19 22 86.36
chip_sw_flash_ctrl_lc_rw_en 156.920s 3167.365us 0 1 0.00
chip_sw_flash_rma_unlocked 3691.380s 42961.744us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 231.180s 3503.222us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 435.430s 6591.966us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 523.760s 6379.927us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 532.130s 6046.516us 0 1 0.00
chip_sw_lc_ctrl_transition 341.940s 6181.291us 1 1 100.00
chip_sw_keymgr_key_derivation 1478.490s 12363.153us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 300.570s 8924.186us 1 1 100.00
chip_sw_sram_ctrl_execution_main 408.450s 8371.246us 1 1 100.00
chip_prim_tl_access 189.170s 9219.397us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 718.200s 12968.857us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 345.430s 4116.936us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 387.090s 4890.703us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 386.710s 4707.333us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 378.730s 5000.307us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 415.300s 4611.531us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 332.330s 4405.865us 1 1 100.00
chip_tap_straps_dev 129.260s 3297.810us 1 1 100.00
chip_tap_straps_rma 238.120s 4993.197us 1 1 100.00
chip_tap_straps_prod 109.040s 3115.574us 1 1 100.00
chip_rv_dm_lc_disabled 379.190s 13300.412us 0 1 0.00
chip_lc_scrap 4 4 100.00
chip_sw_lc_ctrl_rma_to_scrap 150.670s 3152.883us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 83.940s 3233.872us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 86.320s 3653.787us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 84.240s 2664.026us 1 1 100.00
chip_lc_test_locked 1 2 50.00
chip_sw_lc_walkthrough_testunlocks 1599.650s 25964.669us 1 1 100.00
chip_rv_dm_lc_disabled 379.190s 13300.412us 0 1 0.00
chip_sw_lc_walkthrough 2 5 40.00
chip_sw_lc_walkthrough_dev 599.510s 10317.509us 0 1 0.00
chip_sw_lc_walkthrough_prod 695.020s 12361.418us 0 1 0.00
chip_sw_lc_walkthrough_prodend 666.850s 11460.371us 1 1 100.00
chip_sw_lc_walkthrough_rma 429.460s 6861.755us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 1599.650s 25964.669us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 2 3 66.67
chip_sw_lc_ctrl_volatile_raw_unlock 65.270s 2109.026us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 58.960s 1959.272us 1 1 100.00
rom_volatile_raw_unlock 50.317s 0.000us 0 1 0.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 3507.260s 17237.963us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3731.770s 19458.560us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 611.200s 5642.102us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 611.200s 5642.102us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 611.200s 5642.102us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 313.810s 3389.806us 1 1 100.00
chip_otp_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 341.940s 6181.291us 1 1 100.00
chip_sw_otp_ctrl_keys 5 5 100.00
chip_sw_flash_init 1211.860s 20434.741us 1 1 100.00
chip_sw_otbn_mem_scramble 313.810s 3389.806us 1 1 100.00
chip_sw_keymgr_key_derivation 1478.490s 12363.153us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 432.680s 4885.817us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 179.020s 3414.157us 1 1 100.00
chip_sw_otp_ctrl_entropy 5 5 100.00
chip_sw_flash_init 1211.860s 20434.741us 1 1 100.00
chip_sw_otbn_mem_scramble 313.810s 3389.806us 1 1 100.00
chip_sw_keymgr_key_derivation 1478.490s 12363.153us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 432.680s 4885.817us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 179.020s 3414.157us 1 1 100.00
chip_sw_otp_ctrl_program 1 1 100.00
chip_sw_lc_ctrl_transition 341.940s 6181.291us 1 1 100.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 332.420s 4569.749us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 162.700s 2500.768us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 5 6 83.33
chip_sw_otp_ctrl_lc_signals_test_unlocked0 231.180s 3503.222us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 435.430s 6591.966us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 523.760s 6379.927us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 532.130s 6046.516us 0 1 0.00
chip_sw_lc_ctrl_transition 341.940s 6181.291us 1 1 100.00
chip_prim_tl_access 189.170s 9219.397us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 189.170s 9219.397us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 899.200s 7631.333us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 1 1 100.00
chip_sw_pwrmgr_full_aon_reset 350.970s 9636.812us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1357.320s 28170.751us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 251.470s 6985.565us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 0 1 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 312.800s 7693.898us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 414.820s 7421.001us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1114.000s 23378.033us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 1 2 50.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 181.000s 5921.332us 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 596.160s 8542.690us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 866.710s 12901.856us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 427.930s 5459.868us 1 1 100.00
chip_sw_pwrmgr_aon_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_full_aon_reset 350.970s 9636.812us 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 230.310s 4474.127us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 729.510s 9443.249us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 259.780s 6237.551us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 180.150s 3471.559us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 230.010s 5306.408us 0 1 0.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 746.820s 8905.302us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1020.220s 11081.892us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1737.540s 22722.439us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 156.450s 2760.891us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 434.900s 6153.968us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 300.570s 8924.186us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 300.570s 8924.186us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 3 4 75.00
chip_sw_pwrmgr_all_reset_reqs 1020.220s 11081.892us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 230.010s 5306.408us 0 1 0.00
chip_sw_pwrmgr_wdog_reset 427.930s 5459.868us 1 1 100.00
chip_sw_pwrmgr_smoketest 199.590s 5407.616us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 244.920s 4095.587us 1 1 100.00
chip_sw_rstmgr_cpu_info 1 1 100.00
chip_sw_rstmgr_cpu_info 470.060s 7734.626us 1 1 100.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 219.640s 3236.763us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 1169.010s 15248.989us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 137.360s 3023.799us 1 1 100.00
chip_sw_rstmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 434.900s 6153.968us 1 1 100.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1088.570s 8373.291us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 448.830s 4801.548us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 482.320s 4754.607us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 184.760s 3254.861us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 179.020s 3414.157us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 1 1 100.00
chip_sw_rstmgr_cpu_info 470.060s 7734.626us 1 1 100.00
chip_sw_rv_core_ibex_double_fault 1 1 100.00
chip_sw_rstmgr_cpu_info 470.060s 7734.626us 1 1 100.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 1683.080s 22053.838us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 927.160s 13610.828us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 244.920s 4095.587us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 190.870s 3527.331us 0 1 0.00
chip_rv_dm_access_after_wakeup 1 1 100.00
chip_sw_rv_dm_access_after_wakeup 273.810s 5659.838us 1 1 100.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 238.120s 4993.197us 1 1 100.00
chip_rv_dm_lc_disabled 0 1 0.00
chip_rv_dm_lc_disabled 379.190s 13300.412us 0 1 0.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 531.390s 5414.866us 1 1 100.00
chip_plic_all_irqs_10 250.960s 3824.782us 1 1 100.00
chip_plic_all_irqs_20 414.500s 5112.564us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 193.660s 3704.455us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 196.770s 3140.573us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 3104.440s 15060.474us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 437.840s 7196.257us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 170.410s 3339.134us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 215.510s 3561.462us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 183.500s 2899.769us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 432.680s 4885.817us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 399.580s 4622.874us 1 1 100.00
chip_sw_sleep_sram_ret_contents 2 2 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 420.910s 8388.909us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 355.430s 7178.385us 1 1 100.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 408.450s 8371.246us 1 1 100.00
chip_sw_sram_lc_escalation 2 2 100.00
chip_sw_all_escalation_resets 434.900s 6153.968us 1 1 100.00
chip_sw_data_integrity_escalation 382.390s 4995.140us 1 1 100.00
chip_sw_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 746.820s 8905.302us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1035.590s 24513.139us 1 1 100.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 151.660s 2760.980us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 212.570s 3570.391us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 319.200s 4635.486us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 1 1 100.00
chip_sw_sysrst_ctrl_reset 1035.590s 24513.139us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_reset 1 1 100.00
chip_sw_sysrst_ctrl_reset 1035.590s 24513.139us 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2479.770s 20767.413us 1 1 100.00
chip_sw_sysrst_ctrl_flash_wp_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2479.770s 20767.413us 1 1 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 372.150s 7191.132us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3126.270s 35414.702us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 134.730s 3018.449us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 179.580s 3112.321us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 263.270s 3932.813us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 268.690s 3397.538us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 992.340s 8564.107us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 5435.150s 31668.984us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 1808.860s 11487.545us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 171.310s 3212.123us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 166.210s 3155.017us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 95.660s 2877.789us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 10183.760s 71864.597us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 1076.660s 6391.458us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 413.790s 6772.264us 0 1 0.00
rom_e2e_jtag_debug_dev 158.070s 4444.033us 0 1 0.00
rom_e2e_jtag_debug_rma 365.880s 6268.847us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 62.400s 2591.375us 0 1 0.00
rom_e2e_jtag_inject_dev 57.540s 2513.745us 0 1 0.00
rom_e2e_jtag_inject_rma 58.470s 2548.855us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 59.861s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 1 0.00
chip_sw_clkmgr_jitter_frequency 280.600s 3707.054us 0 1 0.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 316.930s 2717.545us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 497.350s 4260.884us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 1520.090s 10624.539us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 232.090s 2747.955us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 645.060s 5156.363us 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 62.620s 2265.456us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 155.950s 3731.858us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 1 1 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 326.660s 6081.732us 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 303.700s 5464.311us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1020.220s 11081.892us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 413.790s 6772.264us 0 1 0.00
rom_e2e_jtag_debug_dev 158.070s 4444.033us 0 1 0.00
rom_e2e_jtag_debug_rma 365.880s 6268.847us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 357.080s 5408.247us 1 1 100.00
chip_sw_plic_alerts 1 1 100.00
chip_sw_all_escalation_resets 434.900s 6153.968us 1 1 100.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 5884.570s 38307.639us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 5884.570s 38307.639us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 192.040s 4248.611us 1 1 100.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 365.660s 4692.372us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 3049.690s 18356.758us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 8 10 80.00
chip_sival_flash_info_access 221.010s 3587.897us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 368.460s 5629.438us 1 1 100.00
chip_sw_otp_ctrl_rot_auth_config 5.760s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 125.500s 3019.311us 1 1 100.00
chip_sw_otp_ctrl_descrambling 193.740s 2889.260us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 250.640s 3849.859us 1 1 100.00
chip_sw_pwrmgr_sleep_wake_5_bug 8.616s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 197.380s 3330.880us 1 1 100.00
ate_bootstrap_flash_erase 6208.430s 45124.003us 1 1 100.00
ate_bootstrap_disjoint 10096.670s 84869.625us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(!$isunknown(pin_wkup_req_o))'
chip_sw_sleep_pin_wake 2136673025774389577605057953427456561004461778511964209903211928743068291929 318
UVM_ERROR @ 3333.384000 us: (pinmux.sv:662) [ASSERT FAILED] AonWkupReqKnownO_A
UVM_INFO @ 3333.384000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
chip_sw_spi_device_pass_through_collision 75185841533163539154434263044398155516381712656005531798876646711389351988906 320
UVM_INFO @ 3339.133810 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_flash_ctrl_lc_rw_en 54923540713648228192691938088023547913535794283905815152871729686141104047023 309
UVM_INFO @ 3167.364934 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *
chip_sw_otp_ctrl_lc_signals_rma 69470315387845816867145338383682590170869476896303786030469712407996530687432 342
UVM_INFO @ 6046.515826 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
chip_sw_otp_ctrl_escalation 42439336382705614492771596323781109643437626473123821036940694611677899980886 316
UVM_ERROR @ 3731.858190 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3731.858190 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_csrng_fuse_en_sw_app_read_test 93360930681054694372700619867738224855789803309214679178631880163921675906526 312
UVM_ERROR @ 3110.266512 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3110.266512 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode
chip_sw_otp_ctrl_rot_auth_config 9625856254163006743544553902347917878661738428321275764178363416030735704169 282
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_lc_walkthrough_dev 25571243194330793577887358625805024122499377938352430612646757861435775179284 369
UVM_INFO @ 10317.508917 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 64895113642257605797470616445544311295426869607357439107977882970943650595566 369
UVM_INFO @ 12361.417734 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 26052638267619407589383830107531896303265830443148349236505669850959779760796 341
UVM_INFO @ 6861.754532 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))'
chip_sw_pwrmgr_random_sleep_all_reset_reqs 59607117773070691610750272229455164393534485540300914869987862636486588493159 315
UVM_ERROR @ 5306.408000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 5306.408000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 94077403254479341349526867314730768088504906566407439091883914913999506587074 314
UVM_ERROR @ 5921.332000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 5921.332000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 19087910506347658305465498711801370825004267569221898506196096839884308426846 325
UVM_ERROR @ 7693.898000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7693.898000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))'
chip_sw_pwrmgr_sleep_power_glitch_reset 1754847531481048617036706281485231205842906442544141175337036387775473335421 313
UVM_ERROR @ 3471.559150 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 3471.559150 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 16677700009493637500321706811706961763781793697612118791682228481694070638189 339
UVM_ERROR @ 9443.248507 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 9443.248507 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 38667907113702920439547202562844250053178731067068803846365286163964760227217 332
UVM_INFO @ 35414.701874 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *!
chip_sw_alert_test 93960728347542228769864584470919811349098573290041999768409546800004883517958 307
UVM_INFO @ 3267.563452 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
chip_sw_alert_handler_lpg_sleep_mode_alerts 110925518904892624527509051849450645832492696300343440273801888370599696434012 308
UVM_INFO @ 2608.112381 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job killed!
chip_sw_alert_handler_lpg_sleep_mode_pings 20467725223534845820104751200697932324950297200208777908442570826948309236525 None
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *).
chip_tl_errors 115459022826965015624006905701870689569654337999615821048224068754083965639443 217
TL item was: req: (cip_tl_seq_item@38613) { a_addr: 'h106f8 a_data: 'hbf021b75 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h32 a_opcode: 'h4 a_user: 'h1ae12 d_param: 'h0 d_source: 'h32 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2102.301900 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_clkmgr_jitter_frequency 97141915543957046030409665287086396133735337400391749668348078633601521050842 343
UVM_INFO @ 3707.054224 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']
chip_sw_pwrmgr_sleep_wake_5_bug 59510793554148227550473657512595759412988072661058902563078399754050185892165 None
---- STDERR ----
Another command (pid=2067690) is running. Waiting for it to complete on the server (server_pid=283649)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 90395991375747680786544663438851682150606400995954574329294963297749892182335 None
Another command (pid=558322) is running. Waiting for it to complete on the server (server_pid=283649)...
Another command (pid=398000) is running. Waiting for it to complete on the server (server_pid=283649)...
Another command (pid=586157) is running. Waiting for it to complete on the server (server_pid=283649)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_dev 49155869130733899123057077038679137573941990809808561724636547859638935853017 None
Another command (pid=446814) is running. Waiting for it to complete on the server (server_pid=283649)...
Another command (pid=545258) is running. Waiting for it to complete on the server (server_pid=283649)...
Another command (pid=537845) is running. Waiting for it to complete on the server (server_pid=283649)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod 34945526929893585142675681559020485934742003707679167107568499331712126043031 None
---- STDERR ----
Another command (pid=446362) is running. Waiting for it to complete on the server (server_pid=283649)...
Another command (pid=458089) is running. Waiting for it to complete on the server (server_pid=283649)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 110953766681106692701461495841118509124753964598549455278023196961554180340667 None
Another command (pid=567613) is running. Waiting for it to complete on the server (server_pid=283649)...
Another command (pid=555847) is running. Waiting for it to complete on the server (server_pid=283649)...
Another command (pid=460162) is running. Waiting for it to complete on the server (server_pid=283649)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_rma 104271796600349427911477070225168025098347476202297947761260146725000769061874 None
Another command (pid=443935) is running. Waiting for it to complete on the server (server_pid=283649)...
Another command (pid=442307) is running. Waiting for it to complete on the server (server_pid=283649)...
Another command (pid=444726) is running. Waiting for it to complete on the server (server_pid=283649)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 2457626805535098236960105253756711764740646121439492183967891921347083904486 None
Another command (pid=355526) is running. Waiting for it to complete on the server (server_pid=283649)...
Another command (pid=350423) is running. Waiting for it to complete on the server (server_pid=283649)...
Another command (pid=381270) is running. Waiting for it to complete on the server (server_pid=283649)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_dev 53399736860779259829261756303265515566149990536604102130551785487136476631533 None
Another command (pid=612677) is running. Waiting for it to complete on the server (server_pid=283649)...
Another command (pid=615880) is running. Waiting for it to complete on the server (server_pid=283649)...
Another command (pid=631026) is running. Waiting for it to complete on the server (server_pid=283649)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod 86687235283941705577687698852093914863393634707107075402373485629505292916452 None
Another command (pid=536789) is running. Waiting for it to complete on the server (server_pid=283649)...
Another command (pid=523340) is running. Waiting for it to complete on the server (server_pid=283649)...
Another command (pid=567613) is running. Waiting for it to complete on the server (server_pid=283649)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 39835656215560587751332033875972909261487949313111711365467055971777784344117 None
Another command (pid=445594) is running. Waiting for it to complete on the server (server_pid=283649)...
Another command (pid=567613) is running. Waiting for it to complete on the server (server_pid=283649)...
Another command (pid=555847) is running. Waiting for it to complete on the server (server_pid=283649)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_rma 77312495536956710506220198210196343919831946051425045275419622456298467077173 None
Another command (pid=567613) is running. Waiting for it to complete on the server (server_pid=283649)...
Another command (pid=538380) is running. Waiting for it to complete on the server (server_pid=283649)...
Another command (pid=555847) is running. Waiting for it to complete on the server (server_pid=283649)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 48236934527235354711418409071697860537950672875690133957556142969712956692161 None
---- STDERR ----
Another command (pid=436327) is running. Waiting for it to complete on the server (server_pid=283649)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_dev 50867089362432365692155885415398997204369409231444344933815473341258274987877 None
---- STDERR ----
Another command (pid=523340) is running. Waiting for it to complete on the server (server_pid=283649)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod 42255846154812020945774600266337298031695546788904652401870727805732614451824 None
Another command (pid=455334) is running. Waiting for it to complete on the server (server_pid=283649)...
Another command (pid=523340) is running. Waiting for it to complete on the server (server_pid=283649)...
Another command (pid=567613) is running. Waiting for it to complete on the server (server_pid=283649)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 70086975917292075221360956810951558641565828052733609951338198574640418714672 None
Another command (pid=446814) is running. Waiting for it to complete on the server (server_pid=283649)...
Another command (pid=545258) is running. Waiting for it to complete on the server (server_pid=283649)...
Another command (pid=537845) is running. Waiting for it to complete on the server (server_pid=283649)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_rma 83333030946197210185115404211805284611634564803326486989108292921169239951396 None
---- STDERR ----
Another command (pid=671976) is running. Waiting for it to complete on the server (server_pid=283649)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_test_unlocked0 4828189392810440718884344610156627408243215442232012397620576174499386855892 None
Another command (pid=373492) is running. Waiting for it to complete on the server (server_pid=283649)...
Another command (pid=355526) is running. Waiting for it to complete on the server (server_pid=283649)...
Another command (pid=350423) is running. Waiting for it to complete on the server (server_pid=283649)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_dev 27401444672851281144239630383663138428984660737654329496846023889665700627204 None
Another command (pid=348350) is running. Waiting for it to complete on the server (server_pid=283649)...
Another command (pid=373492) is running. Waiting for it to complete on the server (server_pid=283649)...
Another command (pid=355526) is running. Waiting for it to complete on the server (server_pid=283649)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod 77703602207007843206208759182966813647397274648619010188889691982107552908696 None
Another command (pid=770370) is running. Waiting for it to complete on the server (server_pid=283649)...
Another command (pid=803280) is running. Waiting for it to complete on the server (server_pid=283649)...
Another command (pid=808119) is running. Waiting for it to complete on the server (server_pid=283649)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod_end 19391749312780328212171048404508460492843477600466666160158694450598244720318 None
Another command (pid=407497) is running. Waiting for it to complete on the server (server_pid=283649)...
Another command (pid=422622) is running. Waiting for it to complete on the server (server_pid=283649)...
Another command (pid=438221) is running. Waiting for it to complete on the server (server_pid=283649)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_rma 36023333354088215574179109873192800298685038040807820503931444960578458773523 None
Another command (pid=436327) is running. Waiting for it to complete on the server (server_pid=283649)...
Another command (pid=348479) is running. Waiting for it to complete on the server (server_pid=283649)...
Another command (pid=407497) is running. Waiting for it to complete on the server (server_pid=283649)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_volatile_raw_unlock 84626414074634936895055062409111501187449025966227697872000696564512192668792 None
Another command (pid=373492) is running. Waiting for it to complete on the server (server_pid=283649)...
Another command (pid=355526) is running. Waiting for it to complete on the server (server_pid=283649)...
Another command (pid=407730) is running. Waiting for it to complete on the server (server_pid=283649)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_raw_unlock 114938913288412059594002420980366865886066659044207832440638469440069473040753 None
Another command (pid=436327) is running. Waiting for it to complete on the server (server_pid=283649)...
Another command (pid=348479) is running. Waiting for it to complete on the server (server_pid=283649)...
Another command (pid=384621) is running. Waiting for it to complete on the server (server_pid=283649)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 110757656342778520851042500118464908898868228042823927715050145617728913415051 None
Another command (pid=348479) is running. Waiting for it to complete on the server (server_pid=283649)...
Another command (pid=407497) is running. Waiting for it to complete on the server (server_pid=283649)...
Another command (pid=380479) is running. Waiting for it to complete on the server (server_pid=283649)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 62092802271532843865777059960887631257096886591386931219737927447007694725685 327
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_test_unlocked0 103597119174978450859063456733046553585121562082122769004386714984807552915161 352
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_dev 95743403840041759786261205616622689393397617345510099410835672332293105586268 319
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 60891502630905293445050202126295328364501738608147430983447710838517920730661 352
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 20938176621295773250491136760434878811196447658832858691807288021137757962193 303
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 54175906003847269253531643076623845980245005422255389172744549028022981055363 305
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 36587197861567262099117274324602437103387208525850667318485388205778743589746 303
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_ERROR @ * us: (cip_base_vseq.sv:649) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch
chip_rv_dm_lc_disabled 71284620391437747274295942867039495303464112323850908167335833844353294631509 270
UVM_INFO @ 13300.411644 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_idle_load 35081192834689508250700510363213596991045899366641625088711755101534896913083 312
UVM_INFO @ 3530.940500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_sleep_load 99338966531437949346119280783899136441999594226950336617847533036232275206545 318
UVM_INFO @ 3647.612500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *
chip_sw_ast_clk_rst_inputs 47498305305555888062602745055794519267192242073741414986529593059204705579928 327
UVM_INFO @ 13552.018650 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 9175212964330824169204570308584251162233069109515753113791787386148770258247 362
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 81938781587850334829791843392287467125605333296065156355899380899923126599270 325
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_dev 21431562699522558249702581598882427426522969436975356968330202247369286378196 366
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_dev 20269128529827503116695083179627721242647274615269425008731108000696640789094 328
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_prod 16850454528065358244629158752014629845532200421291484334207038518812794430957 368
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 104567045299692416633515747326132796883974881930471625367922108761895457968109 365
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_rma 95404533764878271689040345745545075905666919154230488011793558444463045669375 368
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod 24274701752443537477456596584164222659483440192943085306810190658128071331064 327
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 89374251990045871040600071510542104257242390261297850838522934879148047414148 328
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_rma 58171899705776195562645988752915235319718943841428296797024427560585991353321 328
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 112756311089176774992231072610239698376710411824218544820108662650272698405953 325
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_dev 114365415920077328364461263011217401625675098612959887584219496678388686214484 327
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_prod 7655740839756951387973556091333872624289501915877339958309365325931636976586 325
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 35382538683840887752989149350622635118997156452974234660278282587868858305353 325
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_rma 14305904742574557705713111901458123759916354600734905636751014133214818216798 325
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)'
rom_keymgr_functest 100699852730743099215691773561580376930611930778763505154080515046222822842316 327
UVM_ERROR @ 5268.627194 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 5268.627194 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---