Simulation Results: clkmgr

 
17/04/2026 01:26:32 DVSim: v1.31.0 sha: ee0af46 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.61 %
  • code
  • 97.88 %
  • assert
  • 94.35 %
  • func
  • 85.59 %
  • line
  • 98.89 %
  • branch
  • 98.62 %
  • cond
  • 92.70 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.900s 89.977us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.840s 26.863us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.670s 15.114us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 6.790s 1344.613us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.620s 224.180us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.280s 287.473us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.670s 15.114us 1 1 100.00
clkmgr_csr_aliasing 1.620s 224.180us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.750s 54.903us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.700s 25.041us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.840s 48.986us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.830s 49.415us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.900s 89.977us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 4.420s 1546.435us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 5.280s 2009.367us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 4.420s 1546.435us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 56.120s 12114.704us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.870s 37.753us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 2.820s 556.482us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 2.820s 556.482us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.840s 26.863us 1 1 100.00
clkmgr_csr_rw 0.670s 15.114us 1 1 100.00
clkmgr_csr_aliasing 1.620s 224.180us 1 1 100.00
clkmgr_same_csr_outstanding 1.050s 47.836us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.840s 26.863us 1 1 100.00
clkmgr_csr_rw 0.670s 15.114us 1 1 100.00
clkmgr_csr_aliasing 1.620s 224.180us 1 1 100.00
clkmgr_same_csr_outstanding 1.050s 47.836us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 0.700s 14.837us 0 1 0.00
clkmgr_tl_intg_err 1.540s 218.980us 1 1 100.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.120s 94.283us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.120s 94.283us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.120s 94.283us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.120s 94.283us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 1.390s 79.987us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 1.540s 218.980us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 4.420s 1546.435us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 5.280s 2009.367us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.120s 94.283us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.880s 41.205us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 1.190s 76.761us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.740s 49.466us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.960s 67.935us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.810s 64.205us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.670s 15.114us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 0.700s 14.837us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.670s 15.114us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.670s 15.114us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 0.700s 14.837us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 4.010s 909.256us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 27.170s 5409.262us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.fatal_err_code.shadow_storage_err reset value: * Write_and_check_update_error task: check storage_err status
clkmgr_shadow_reg_errors_with_csr_rw 84091436377450046296710334104501090791208268315356008424917322264792658635447 76
UVM_INFO @ 79987344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire
clkmgr_sec_cm 74024038231162246134510859160326702592287497681430499593706124112500857420662 84
UVM_INFO @ 14836755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---