Simulation Results: csrng

 
17/04/2026 01:26:32 DVSim: v1.31.0 sha: ee0af46 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.25 %
  • code
  • 92.38 %
  • assert
  • 93.45 %
  • func
  • 72.92 %
  • block
  • 97.05 %
  • line
  • 97.80 %
  • branch
  • 92.59 %
  • toggle
  • 93.44 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
91.67%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 3.000s 82.274us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 62.258us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 1.000s 42.381us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 10.000s 430.730us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 4.000s 176.347us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 1.000s 38.145us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 1.000s 42.381us 1 1 100.00
csrng_csr_aliasing 4.000s 176.347us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 5.000s 97.984us 1 1 100.00
alerts 1 1 100.00
csrng_alert 15.000s 847.678us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 26.891us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 3.000s 124.284us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 3.000s 124.284us 0 1 0.00
stress_all 1 1 100.00
csrng_stress_all 20.000s 532.500us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 28.661us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 40.757us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 5.000s 226.059us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 5.000s 226.059us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 62.258us 1 1 100.00
csrng_csr_rw 1.000s 42.381us 1 1 100.00
csrng_csr_aliasing 4.000s 176.347us 1 1 100.00
csrng_same_csr_outstanding 2.000s 52.532us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 62.258us 1 1 100.00
csrng_csr_rw 1.000s 42.381us 1 1 100.00
csrng_csr_aliasing 4.000s 176.347us 1 1 100.00
csrng_same_csr_outstanding 2.000s 52.532us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 2.000s 44.754us 1 1 100.00
csrng_tl_intg_err 4.000s 234.131us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_regwen 2.000s 52.626us 1 1 100.00
csrng_csr_rw 1.000s 42.381us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 15.000s 847.678us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 20.000s 532.500us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 5.000s 97.984us 1 1 100.00
csrng_err 2.000s 26.891us 1 1 100.00
csrng_sec_cm 2.000s 44.754us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 5.000s 97.984us 1 1 100.00
csrng_err 2.000s 26.891us 1 1 100.00
csrng_sec_cm 2.000s 44.754us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 5.000s 97.984us 1 1 100.00
csrng_err 2.000s 26.891us 1 1 100.00
csrng_sec_cm 2.000s 44.754us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 5.000s 97.984us 1 1 100.00
csrng_err 2.000s 26.891us 1 1 100.00
csrng_sec_cm 2.000s 44.754us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 5.000s 97.984us 1 1 100.00
csrng_err 2.000s 26.891us 1 1 100.00
csrng_sec_cm 2.000s 44.754us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 15.000s 847.678us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 5.000s 97.984us 1 1 100.00
csrng_err 2.000s 26.891us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 20.000s 532.500us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 15.000s 847.678us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 4.000s 234.131us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 5.000s 97.984us 1 1 100.00
csrng_err 2.000s 26.891us 1 1 100.00
csrng_sec_cm 2.000s 44.754us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 5.000s 97.984us 1 1 100.00
csrng_err 2.000s 26.891us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 5.000s 97.984us 1 1 100.00
csrng_err 2.000s 26.891us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 5.000s 97.984us 1 1 100.00
csrng_err 2.000s 26.891us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 5.000s 97.984us 1 1 100.00
csrng_err 2.000s 26.891us 1 1 100.00
csrng_sec_cm 2.000s 44.754us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 5.000s 97.984us 1 1 100.00
csrng_err 2.000s 26.891us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 0.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:660) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*])
csrng_cmds 32044664187987255880462555315961530594760541484579871845150145576928947741105 130
UVM_INFO @ 124283579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job killed!
csrng_stress_all_with_rand_reset 61580095529698564621982132002701091844212770225408013303320806282064372890181 None