Simulation Results: edn/edn0

 
17/04/2026 01:26:32 DVSim: v1.31.0 sha: ee0af46 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.96 %
  • code
  • 76.21 %
  • assert
  • 93.71 %
  • func
  • 78.97 %
  • line
  • 96.52 %
  • branch
  • 87.59 %
  • cond
  • 82.47 %
  • toggle
  • 69.87 %
  • FSM
  • 44.62 %
Validation stages
V1
100.00%
V2
92.86%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.830s 25.629us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.770s 25.060us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.950s 18.468us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.120s 232.362us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.080s 19.994us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.920s 63.108us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.950s 18.468us 1 1 100.00
edn_csr_aliasing 1.080s 19.994us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 2.030s 238.779us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 2.030s 238.779us 1 1 100.00
genbits 1 1 100.00
edn_genbits 2.030s 238.779us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.880s 34.232us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.250s 70.124us 1 1 100.00
errs 1 1 100.00
edn_err 0.920s 18.389us 1 1 100.00
disable 1 2 50.00
edn_disable 0.910s 24.037us 1 1 100.00
edn_disable_auto_req_mode 4.190s 500.000us 0 1 0.00
stress_all 1 1 100.00
edn_stress_all 2.100s 417.480us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.830s 13.189us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.750s 50.220us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.800s 237.553us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.800s 237.553us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.770s 25.060us 1 1 100.00
edn_csr_rw 0.950s 18.468us 1 1 100.00
edn_csr_aliasing 1.080s 19.994us 1 1 100.00
edn_same_csr_outstanding 1.300s 36.460us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.770s 25.060us 1 1 100.00
edn_csr_rw 0.950s 18.468us 1 1 100.00
edn_csr_aliasing 1.080s 19.994us 1 1 100.00
edn_same_csr_outstanding 1.300s 36.460us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 7.190s 986.948us 1 1 100.00
edn_tl_intg_err 1.560s 69.927us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.840s 18.852us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.250s 70.124us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.190s 986.948us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.190s 986.948us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 7.190s 986.948us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 7.190s 986.948us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.250s 70.124us 1 1 100.00
edn_sec_cm 7.190s 986.948us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.250s 70.124us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.560s 69.927us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 29.460s 7550.396us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
edn_disable_auto_req_mode 39127859371381090939880992608754315509133713668922010680915054459225532486612 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---