Simulation Results: edn/edn1

 
17/04/2026 01:26:32 DVSim: v1.31.0 sha: ee0af46 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.81 %
  • code
  • 84.08 %
  • assert
  • 97.14 %
  • func
  • 79.20 %
  • line
  • 98.10 %
  • branch
  • 93.51 %
  • cond
  • 89.46 %
  • toggle
  • 94.99 %
  • FSM
  • 44.32 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.750s 44.252us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.760s 15.800us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.760s 25.329us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.410s 257.574us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.200s 75.423us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.020s 177.182us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.760s 25.329us 1 1 100.00
edn_csr_aliasing 1.200s 75.423us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.030s 55.869us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.030s 55.869us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.030s 55.869us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.800s 24.673us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.920s 26.055us 1 1 100.00
errs 1 1 100.00
edn_err 0.810s 125.686us 1 1 100.00
disable 2 2 100.00
edn_disable 0.730s 42.105us 1 1 100.00
edn_disable_auto_req_mode 0.850s 123.753us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.330s 452.479us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.830s 136.821us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.760s 14.423us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.950s 73.596us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.950s 73.596us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.760s 15.800us 1 1 100.00
edn_csr_rw 0.760s 25.329us 1 1 100.00
edn_csr_aliasing 1.200s 75.423us 1 1 100.00
edn_same_csr_outstanding 0.910s 25.143us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.760s 15.800us 1 1 100.00
edn_csr_rw 0.760s 25.329us 1 1 100.00
edn_csr_aliasing 1.200s 75.423us 1 1 100.00
edn_same_csr_outstanding 0.910s 25.143us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.050s 544.461us 1 1 100.00
edn_tl_intg_err 1.750s 1441.434us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.860s 45.627us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.920s 26.055us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.050s 544.461us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.050s 544.461us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.050s 544.461us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.050s 544.461us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.920s 26.055us 1 1 100.00
edn_sec_cm 2.050s 544.461us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.920s 26.055us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.750s 1441.434us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 29.860s 7864.591us 1 1 100.00