Simulation Results: flash_ctrl

 
17/04/2026 01:26:32 DVSim: v1.31.0 sha: ee0af46 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.51 %
  • code
  • 93.97 %
  • assert
  • 96.76 %
  • func
  • 95.79 %
  • line
  • 95.94 %
  • branch
  • 97.14 %
  • cond
  • 93.24 %
  • toggle
  • 97.84 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 76.870s 156.356us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 15.050s 103.033us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 12.740s 31.174us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 9.910s 35.319us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 24.860s 1774.271us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 32.540s 452.219us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 6.560s 279.178us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 9.910s 35.319us 1 1 100.00
flash_ctrl_csr_aliasing 32.540s 452.219us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 9.690s 74.565us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 9.020s 81.664us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 10.970s 27.865us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 18.720s 34.146us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1322.030s 167284.999us 1 1 100.00
flash_ctrl_hw_rma_reset 655.480s 120155.297us 1 1 100.00
flash_ctrl_lcmgr_intg 5.720s 23.455us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1455.010s 553212.822us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 168.860s 1456.826us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 6.290s 38.544us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 1862.180s 364838.142us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 37.590s 296.841us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 16.060s 76.780us 1 1 100.00
flash_ctrl_rw_evict_all_en 12.460s 72.293us 1 1 100.00
flash_ctrl_re_evict 21.330s 687.158us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 93.730s 163.787us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 93.730s 163.787us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 230.730s 5191.340us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 16.930s 3491.667us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 373.210s 478.712us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 584.350s 10958.001us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 270.930s 1790.351us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 743.100s 422.549us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 5.820s 76.897us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 172.180s 8624.776us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 10.580s 22.009us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 6.830s 19.708us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 328.240s 685.806us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 49.760s 1862.666us 1 1 100.00
flash_ctrl_otp_reset 53.700s 43.403us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1322.030s 167284.999us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 118.550s 1154.011us 1 1 100.00
flash_ctrl_intr_wr 60.560s 12236.407us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 197.640s 48517.104us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 164.290s 105406.824us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 39.280s 1984.041us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 41.010s 2679.620us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 13.020s 26.848us 1 1 100.00
flash_ctrl_ro_derr 103.590s 9895.791us 1 1 100.00
flash_ctrl_rw_derr 125.820s 3384.179us 1 1 100.00
flash_ctrl_derr_detect 118.320s 1886.941us 1 1 100.00
flash_ctrl_integrity 450.310s 4370.931us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 14.600s 60.632us 1 1 100.00
flash_ctrl_ro_serr 86.610s 694.801us 1 1 100.00
flash_ctrl_rw_serr 173.940s 7936.669us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 46.800s 747.824us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 38.400s 1075.507us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 128.050s 2414.215us 1 1 100.00
flash_ctrl_write_word_sweep 7.980s 41.061us 1 1 100.00
flash_ctrl_read_word_sweep 6.710s 25.974us 1 1 100.00
flash_ctrl_ro 89.720s 1203.650us 1 1 100.00
flash_ctrl_rw 392.780s 14965.193us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 35.530s 348.258us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 613.400s 159374.087us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 211.120s 10020.135us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 5.830s 53.161us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 7.950s 30.226us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 7.360s 193.947us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 7.360s 193.947us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 12.740s 31.174us 1 1 100.00
flash_ctrl_csr_rw 9.910s 35.319us 1 1 100.00
flash_ctrl_csr_aliasing 32.540s 452.219us 1 1 100.00
flash_ctrl_same_csr_outstanding 9.270s 413.351us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 12.740s 31.174us 1 1 100.00
flash_ctrl_csr_rw 9.910s 35.319us 1 1 100.00
flash_ctrl_csr_aliasing 32.540s 452.219us 1 1 100.00
flash_ctrl_same_csr_outstanding 9.270s 413.351us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 27.950s 171.307us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 27.950s 171.307us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 27.950s 171.307us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 27.950s 171.307us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 27.210s 269.242us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_sec_cm 1512.150s 4885.961us 1 1 100.00
flash_ctrl_tl_intg_err 356.380s 834.025us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 356.380s 834.025us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 356.380s 834.025us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 14.520s 507.469us 1 1 100.00
flash_ctrl_wr_intg 7.200s 774.501us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 76.870s 156.356us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 53.700s 43.403us 1 1 100.00
flash_ctrl_disable 10.580s 22.009us 1 1 100.00
flash_ctrl_sec_info_access 56.030s 5203.245us 1 1 100.00
flash_ctrl_connect 6.830s 19.708us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 5.710s 171.838us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 9.910s 35.319us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 27.950s 171.307us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 9.910s 35.319us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 27.950s 171.307us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 9.910s 35.319us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 27.950s 171.307us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 10.580s 22.009us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 14.520s 507.469us 1 1 100.00
flash_ctrl_access_after_disable 5.540s 19.762us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 13.730s 26.942us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 10.580s 22.009us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 16.930s 3491.667us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 392.780s 14965.193us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 173.940s 7936.669us 1 1 100.00
flash_ctrl_rw_derr 125.820s 3384.179us 1 1 100.00
flash_ctrl_integrity 450.310s 4370.931us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1322.030s 167284.999us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1512.150s 4885.961us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1512.150s 4885.961us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1512.150s 4885.961us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1512.150s 4885.961us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 11.880s 893.757us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 6.130s 71.500us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 11.490s 58.795us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1512.150s 4885.961us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1512.150s 4885.961us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1512.150s 4885.961us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 25.080s 68.713us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 302.040s 3533.546us 1 1 100.00