Simulation Results: hmac

 
17/04/2026 01:26:32 DVSim: v1.31.0 sha: ee0af46 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.32 %
  • code
  • 97.35 %
  • assert
  • 96.70 %
  • func
  • 43.91 %
  • line
  • 99.69 %
  • branch
  • 99.50 %
  • cond
  • 96.40 %
  • toggle
  • 100.00 %
  • FSM
  • 91.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 6.880s 1132.589us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.850s 23.007us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.930s 47.228us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 6.950s 221.848us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 4.560s 1219.580us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.040s 32.289us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.930s 47.228us 1 1 100.00
hmac_csr_aliasing 4.560s 1219.580us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 27.510s 701.674us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 63.550s 5983.836us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 222.040s 86877.911us 1 1 100.00
hmac_test_sha384_vectors 400.850s 25491.922us 1 1 100.00
hmac_test_sha512_vectors 417.990s 13264.302us 1 1 100.00
hmac_test_hmac256_vectors 6.350s 1414.299us 1 1 100.00
hmac_test_hmac384_vectors 10.180s 333.631us 1 1 100.00
hmac_test_hmac512_vectors 7.920s 224.700us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 7.000s 270.906us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 149.700s 2628.366us 1 1 100.00
error 1 1 100.00
hmac_error 24.920s 542.970us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 76.180s 7631.842us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 6.880s 1132.589us 1 1 100.00
hmac_long_msg 27.510s 701.674us 1 1 100.00
hmac_back_pressure 63.550s 5983.836us 1 1 100.00
hmac_datapath_stress 149.700s 2628.366us 1 1 100.00
hmac_burst_wr 7.000s 270.906us 1 1 100.00
hmac_stress_all 167.920s 139359.314us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 6.880s 1132.589us 1 1 100.00
hmac_long_msg 27.510s 701.674us 1 1 100.00
hmac_back_pressure 63.550s 5983.836us 1 1 100.00
hmac_datapath_stress 149.700s 2628.366us 1 1 100.00
hmac_wipe_secret 76.180s 7631.842us 1 1 100.00
hmac_test_sha256_vectors 222.040s 86877.911us 1 1 100.00
hmac_test_sha384_vectors 400.850s 25491.922us 1 1 100.00
hmac_test_sha512_vectors 417.990s 13264.302us 1 1 100.00
hmac_test_hmac256_vectors 6.350s 1414.299us 1 1 100.00
hmac_test_hmac384_vectors 10.180s 333.631us 1 1 100.00
hmac_test_hmac512_vectors 7.920s 224.700us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 6.880s 1132.589us 1 1 100.00
hmac_long_msg 27.510s 701.674us 1 1 100.00
hmac_back_pressure 63.550s 5983.836us 1 1 100.00
hmac_datapath_stress 149.700s 2628.366us 1 1 100.00
hmac_burst_wr 7.000s 270.906us 1 1 100.00
hmac_error 24.920s 542.970us 1 1 100.00
hmac_wipe_secret 76.180s 7631.842us 1 1 100.00
hmac_test_sha256_vectors 222.040s 86877.911us 1 1 100.00
hmac_test_sha384_vectors 400.850s 25491.922us 1 1 100.00
hmac_test_sha512_vectors 417.990s 13264.302us 1 1 100.00
hmac_test_hmac256_vectors 6.350s 1414.299us 1 1 100.00
hmac_test_hmac384_vectors 10.180s 333.631us 1 1 100.00
hmac_test_hmac512_vectors 7.920s 224.700us 1 1 100.00
hmac_stress_all 167.920s 139359.314us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 167.920s 139359.314us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.670s 107.156us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.610s 25.997us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.140s 1442.363us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.140s 1442.363us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.850s 23.007us 1 1 100.00
hmac_csr_rw 0.930s 47.228us 1 1 100.00
hmac_csr_aliasing 4.560s 1219.580us 1 1 100.00
hmac_same_csr_outstanding 1.590s 119.865us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.850s 23.007us 1 1 100.00
hmac_csr_rw 0.930s 47.228us 1 1 100.00
hmac_csr_aliasing 4.560s 1219.580us 1 1 100.00
hmac_same_csr_outstanding 1.590s 119.865us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.900s 82.354us 1 1 100.00
hmac_tl_intg_err 3.540s 484.685us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 3.540s 484.685us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 6.880s 1132.589us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 3.900s 696.528us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 24.330s 1413.934us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 0.770s 83.476us 1 1 100.00