Simulation Results: i2c

 
17/04/2026 01:26:32 DVSim: v1.31.0 sha: ee0af46 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.10 %
  • code
  • 81.21 %
  • assert
  • 96.19 %
  • func
  • 77.91 %
  • line
  • 96.35 %
  • branch
  • 92.19 %
  • cond
  • 84.97 %
  • toggle
  • 89.66 %
  • FSM
  • 42.86 %
Validation stages
V1
100.00%
V2
85.37%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 39.900s 4621.345us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 10.890s 2178.246us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 0.850s 40.578us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 0.950s 43.359us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 3.600s 2163.457us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 1.330s 29.354us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 1.140s 142.224us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 0.950s 43.359us 1 1 100.00
i2c_csr_aliasing 1.330s 29.354us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 0 1 0.00
i2c_host_error_intr 1.050s 49.108us 0 1 0.00
host_stress_all 0 1 0.00
i2c_host_stress_all 410.770s 13870.583us 0 1 0.00
host_maxperf 1 1 100.00
i2c_host_perf 27.100s 3265.460us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 0.810s 39.332us 1 1 100.00
host_fifo_watermark 1 1 100.00
i2c_host_fifo_watermark 51.360s 12388.022us 1 1 100.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 93.950s 2334.550us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 0.920s 115.820us 1 1 100.00
i2c_host_fifo_fmt_empty 4.510s 681.663us 1 1 100.00
i2c_host_fifo_reset_rx 4.440s 220.761us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 29.100s 4460.120us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 7.150s 569.281us 1 1 100.00
i2c_host_mode_toggle 0 1 0.00
i2c_host_mode_toggle 3.510s 105.162us 0 1 0.00
target_glitch 0 1 0.00
i2c_target_glitch 2.010s 1730.855us 0 1 0.00
target_stress_all 1 1 100.00
i2c_target_stress_all 69.380s 36487.340us 1 1 100.00
target_maxperf 1 1 100.00
i2c_target_perf 4.280s 1724.860us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 7.310s 1130.468us 1 1 100.00
i2c_target_intr_smoke 4.870s 3727.063us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 1.100s 446.931us 1 1 100.00
i2c_target_fifo_reset_tx 1.080s 346.133us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 400.070s 43653.521us 1 1 100.00
i2c_target_stress_rd 7.310s 1130.468us 1 1 100.00
i2c_target_intr_stress_wr 4.240s 10000.168us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 3.830s 970.974us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 2.020s 386.569us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 4.010s 4192.627us 1 1 100.00
target_mode_glitch 0 1 0.00
i2c_target_hrst 4.990s 11199.744us 0 1 0.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 2.170s 1061.081us 1 1 100.00
i2c_target_fifo_watermarks_tx 1.190s 175.086us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 27.100s 3265.460us 1 1 100.00
i2c_host_perf_precise 13.140s 1577.313us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 7.150s 569.281us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 3.140s 280.265us 1 1 100.00
target_mode_nack_generation 2 3 66.67
i2c_target_nack_acqfull 3.190s 452.341us 1 1 100.00
i2c_target_nack_acqfull_addr 2.530s 2725.931us 1 1 100.00
i2c_target_nack_txstretch 1.080s 271.368us 0 1 0.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 15.900s 1003.403us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 1.710s 1768.584us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 0.760s 27.026us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 0.800s 45.640us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 1.410s 236.799us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 1.410s 236.799us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 0.850s 40.578us 1 1 100.00
i2c_csr_rw 0.950s 43.359us 1 1 100.00
i2c_csr_aliasing 1.330s 29.354us 1 1 100.00
i2c_same_csr_outstanding 1.020s 35.845us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 0.850s 40.578us 1 1 100.00
i2c_csr_rw 0.950s 43.359us 1 1 100.00
i2c_csr_aliasing 1.330s 29.354us 1 1 100.00
i2c_same_csr_outstanding 1.020s 35.845us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_tl_intg_err 1.940s 407.741us 1 1 100.00
i2c_sec_cm 1.490s 545.054us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 1.940s 407.741us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 35.630s 4508.288us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 1.380s 806.252us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 11.870s 6054.510us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
i2c_host_error_intr 109160313152557801507930544662132905030168129562093724374244842774783391283088 94
UVM_INFO @ 49108268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_host_stress_all 76247086861655542176074182236536168360274320632690649969808787605215593785634 126
UVM_INFO @ 13870583123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
i2c_target_glitch 59761361411034655270154761527108029391390237264725743244077953874109450893505 84
UVM_INFO @ 1730854530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*])
i2c_target_unexp_stop 90296740624130965385492938351118079670951225128559481443537074485044245918687 78
UVM_INFO @ 806251816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
i2c_target_hrst 47662696653338448767229074362291013923208261198344966576189249480510077812662 79
UVM_INFO @ 11199744113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
i2c_host_stress_all_with_rand_reset 15663450756212249944092016489517100054247662311716366056195423489155254320677 96
UVM_INFO @ 4508288313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 113694961116162581275375278954642017923457401930241361047505953106884239167738 88
UVM_INFO @ 6054509527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
i2c_host_mode_toggle 83394165600866136354412700914339625997992098523324977007012799822964062137713 87
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: *
i2c_target_nack_txstretch 6459697835603927537174802248190140898329747253992308467018739960235904470595 78
UVM_INFO @ 271368265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---