Simulation Results: keymgr

 
17/04/2026 01:26:32 DVSim: v1.31.0 sha: ee0af46 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.85 %
  • code
  • 94.11 %
  • assert
  • 97.72 %
  • func
  • 62.72 %
  • line
  • 98.68 %
  • branch
  • 97.44 %
  • cond
  • 92.96 %
  • toggle
  • 93.09 %
  • FSM
  • 88.37 %
Validation stages
V1
100.00%
V2
100.00%
V2S
90.91%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_smoke 22.130s 3140.637us 1 1 100.00
random 1 1 100.00
keymgr_random 2.900s 60.528us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 1.040s 268.373us 1 1 100.00
csr_rw 1 1 100.00
keymgr_csr_rw 1.270s 100.574us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 11.290s 1285.919us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 5.690s 536.293us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_csr_mem_rw_with_rand_reset 1.570s 62.523us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_csr_rw 1.270s 100.574us 1 1 100.00
keymgr_csr_aliasing 5.690s 536.293us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 1 1 100.00
keymgr_cfg_regwen 3.310s 123.341us 1 1 100.00
sideload 4 4 100.00
keymgr_sideload 2.780s 85.634us 1 1 100.00
keymgr_sideload_kmac 2.270s 49.956us 1 1 100.00
keymgr_sideload_aes 4.850s 551.076us 1 1 100.00
keymgr_sideload_otbn 3.260s 104.221us 1 1 100.00
direct_to_disabled_state 1 1 100.00
keymgr_direct_to_disabled 2.560s 439.379us 1 1 100.00
lc_disable 1 1 100.00
keymgr_lc_disable 2.690s 59.924us 1 1 100.00
kmac_error_response 1 1 100.00
keymgr_kmac_rsp_err 3.410s 138.036us 1 1 100.00
invalid_sw_input 1 1 100.00
keymgr_sw_invalid_input 22.850s 5458.778us 1 1 100.00
invalid_hw_input 1 1 100.00
keymgr_hwsw_invalid_input 3.850s 300.362us 1 1 100.00
sync_async_fault_cross 1 1 100.00
keymgr_sync_async_fault_cross 2.130s 62.582us 1 1 100.00
stress_all 1 1 100.00
keymgr_stress_all 14.810s 2299.418us 1 1 100.00
intr_test 1 1 100.00
keymgr_intr_test 0.860s 32.851us 1 1 100.00
alert_test 1 1 100.00
keymgr_alert_test 0.770s 15.716us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_tl_errors 1.480s 300.229us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_tl_errors 1.480s 300.229us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_csr_hw_reset 1.040s 268.373us 1 1 100.00
keymgr_csr_rw 1.270s 100.574us 1 1 100.00
keymgr_csr_aliasing 5.690s 536.293us 1 1 100.00
keymgr_same_csr_outstanding 1.330s 22.401us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_csr_hw_reset 1.040s 268.373us 1 1 100.00
keymgr_csr_rw 1.270s 100.574us 1 1 100.00
keymgr_csr_aliasing 5.690s 536.293us 1 1 100.00
keymgr_same_csr_outstanding 1.330s 22.401us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
keymgr_sec_cm 9.270s 2942.611us 1 1 100.00
tl_intg_err 2 2 100.00
keymgr_sec_cm 9.270s 2942.611us 1 1 100.00
keymgr_tl_intg_err 3.700s 2043.771us 1 1 100.00
shadow_reg_update_error 1 1 100.00
keymgr_shadow_reg_errors 2.530s 101.591us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
keymgr_shadow_reg_errors 2.530s 101.591us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
keymgr_shadow_reg_errors 2.530s 101.591us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
keymgr_shadow_reg_errors 2.530s 101.591us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
keymgr_shadow_reg_errors_with_csr_rw 6.980s 630.422us 1 1 100.00
prim_count_check 1 1 100.00
keymgr_sec_cm 9.270s 2942.611us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_sec_cm 9.270s 2942.611us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
keymgr_tl_intg_err 3.700s 2043.771us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
keymgr_shadow_reg_errors 2.530s 101.591us 1 1 100.00
sec_cm_op_config_regwen 1 1 100.00
keymgr_cfg_regwen 3.310s 123.341us 1 1 100.00
sec_cm_reseed_config_regwen 2 2 100.00
keymgr_random 2.900s 60.528us 1 1 100.00
keymgr_csr_rw 1.270s 100.574us 1 1 100.00
sec_cm_sw_binding_config_regwen 2 2 100.00
keymgr_random 2.900s 60.528us 1 1 100.00
keymgr_csr_rw 1.270s 100.574us 1 1 100.00
sec_cm_max_key_ver_config_regwen 2 2 100.00
keymgr_random 2.900s 60.528us 1 1 100.00
keymgr_csr_rw 1.270s 100.574us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
keymgr_lc_disable 2.690s 59.924us 1 1 100.00
sec_cm_constants_consistency 1 1 100.00
keymgr_hwsw_invalid_input 3.850s 300.362us 1 1 100.00
sec_cm_intersig_consistency 1 1 100.00
keymgr_hwsw_invalid_input 3.850s 300.362us 1 1 100.00
sec_cm_hw_key_sw_noaccess 1 1 100.00
keymgr_random 2.900s 60.528us 1 1 100.00
sec_cm_output_keys_ctrl_redun 1 1 100.00
keymgr_sideload_protect 1.870s 57.372us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 9.270s 2942.611us 1 1 100.00
sec_cm_data_fsm_sparse 1 1 100.00
keymgr_sec_cm 9.270s 2942.611us 1 1 100.00
sec_cm_ctrl_fsm_local_esc 1 1 100.00
keymgr_sec_cm 9.270s 2942.611us 1 1 100.00
sec_cm_ctrl_fsm_consistency 0 1 0.00
keymgr_custom_cm 18.250s 10299.732us 0 1 0.00
sec_cm_ctrl_fsm_global_esc 1 1 100.00
keymgr_lc_disable 2.690s 59.924us 1 1 100.00
sec_cm_ctrl_ctr_redun 1 1 100.00
keymgr_sec_cm 9.270s 2942.611us 1 1 100.00
sec_cm_kmac_if_fsm_sparse 1 1 100.00
keymgr_sec_cm 9.270s 2942.611us 1 1 100.00
sec_cm_kmac_if_ctr_redun 1 1 100.00
keymgr_sec_cm 9.270s 2942.611us 1 1 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 0 1 0.00
keymgr_custom_cm 18.250s 10299.732us 0 1 0.00
sec_cm_kmac_if_done_ctrl_consistency 0 1 0.00
keymgr_custom_cm 18.250s 10299.732us 0 1 0.00
sec_cm_reseed_ctr_redun 1 1 100.00
keymgr_sec_cm 9.270s 2942.611us 1 1 100.00
sec_cm_side_load_sel_ctrl_consistency 0 1 0.00
keymgr_custom_cm 18.250s 10299.732us 0 1 0.00
sec_cm_sideload_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 9.270s 2942.611us 1 1 100.00
sec_cm_ctrl_key_integrity 0 1 0.00
keymgr_custom_cm 18.250s 10299.732us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
keymgr_stress_all_with_rand_reset 3.950s 482.216us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (keymgr_custom_cm_vseq.sv:45) [keymgr_custom_cm_vseq] wait timeout occurred!
keymgr_custom_cm 104257775180358599464718924295132630031071880741547520936546514425799912093422 259
UVM_INFO @ 10299732343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
keymgr_stress_all_with_rand_reset 70410814193709693254460796330384746832117608000852080442256051478357466733031 412
UVM_INFO @ 482215603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---