Simulation Results: kmac/unmasked

 
17/04/2026 01:26:32 DVSim: v1.31.0 sha: ee0af46 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.27 %
  • code
  • 89.26 %
  • assert
  • 97.90 %
  • func
  • 92.64 %
  • line
  • 97.36 %
  • branch
  • 95.11 %
  • cond
  • 91.03 %
  • toggle
  • 100.00 %
  • FSM
  • 62.81 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 6.820s 404.161us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.400s 35.490us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 1.120s 27.340us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 8.850s 1540.463us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 4.400s 547.951us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 1.620s 160.920us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 1.120s 27.340us 1 1 100.00
kmac_csr_aliasing 4.400s 547.951us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.850s 73.590us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.420s 126.994us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 590.140s 35942.092us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 582.580s 96531.271us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 29.160s 1859.042us 1 1 100.00
kmac_test_vectors_sha3_256 1581.640s 78362.959us 1 1 100.00
kmac_test_vectors_sha3_384 818.420s 13113.303us 1 1 100.00
kmac_test_vectors_sha3_512 823.140s 77535.849us 1 1 100.00
kmac_test_vectors_shake_128 1433.930s 40395.450us 1 1 100.00
kmac_test_vectors_shake_256 215.900s 30014.220us 1 1 100.00
kmac_test_vectors_kmac 1.470s 121.441us 1 1 100.00
kmac_test_vectors_kmac_xof 2.130s 125.976us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 41.140s 3835.478us 1 1 100.00
app 1 1 100.00
kmac_app 39.130s 5752.561us 1 1 100.00
app_with_partial_data 1 1 100.00
kmac_app_with_partial_data 176.170s 14541.893us 1 1 100.00
entropy_refresh 1 1 100.00
kmac_entropy_refresh 234.660s 25559.210us 1 1 100.00
error 1 1 100.00
kmac_error 123.140s 7994.790us 1 1 100.00
key_error 1 1 100.00
kmac_key_error 16.060s 26965.984us 1 1 100.00
sideload_invalid 1 1 100.00
kmac_sideload_invalid 3.310s 612.774us 1 1 100.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 28.380s 1214.704us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 16.500s 2432.448us 1 1 100.00
entropy_ready_error 1 1 100.00
kmac_entropy_ready_error 23.920s 1526.014us 1 1 100.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.430s 119.875us 1 1 100.00
stress_all 1 1 100.00
kmac_stress_all 189.130s 7178.441us 1 1 100.00
intr_test 1 1 100.00
kmac_intr_test 1.120s 13.969us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 1.100s 21.118us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 1.680s 217.094us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 1.680s 217.094us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 1.400s 35.490us 1 1 100.00
kmac_csr_rw 1.120s 27.340us 1 1 100.00
kmac_csr_aliasing 4.400s 547.951us 1 1 100.00
kmac_same_csr_outstanding 1.590s 36.319us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 1.400s 35.490us 1 1 100.00
kmac_csr_rw 1.120s 27.340us 1 1 100.00
kmac_csr_aliasing 4.400s 547.951us 1 1 100.00
kmac_same_csr_outstanding 1.590s 36.319us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.600s 56.222us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.600s 56.222us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.600s 56.222us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.600s 56.222us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 2.240s 104.266us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_sec_cm 20.490s 6634.122us 1 1 100.00
kmac_tl_intg_err 2.380s 497.697us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 2.380s 497.697us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.430s 119.875us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 6.820s 404.161us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 41.140s 3835.478us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.600s 56.222us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 20.490s 6634.122us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 20.490s 6634.122us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 20.490s 6634.122us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 6.820s 404.161us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.430s 119.875us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 20.490s 6634.122us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 1 1 100.00
kmac_mubi 138.090s 29082.298us 1 1 100.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 6.820s 404.161us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
kmac_stress_all_with_rand_reset 41.400s 2541.215us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
kmac_stress_all_with_rand_reset 30302651253187177589382752750381961893538472796570781129321913630644545078422 129
UVM_INFO @ 2541215309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---