Simulation Results: lc_ctrl/volatile_unlock_disabled

 
17/04/2026 01:26:32 DVSim: v1.31.0 sha: ee0af46 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.94 %
  • code
  • 84.37 %
  • assert
  • 94.13 %
  • func
  • 94.31 %
  • line
  • 97.17 %
  • branch
  • 93.51 %
  • cond
  • 79.38 %
  • toggle
  • 88.24 %
  • FSM
  • 63.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 3.940s 60.446us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.060s 53.565us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.190s 208.870us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.270s 21.903us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.400s 18.092us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.390s 65.292us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.190s 208.870us 1 1 100.00
lc_ctrl_csr_aliasing 1.400s 18.092us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 5.530s 59.724us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 5.560s 217.722us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.050s 27.074us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.810s 308.739us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 8.420s 672.189us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.880s 2030.434us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 8.420s 672.189us 1 1 100.00
lc_ctrl_prog_failure 2.810s 308.739us 1 1 100.00
lc_ctrl_errors 4.880s 2030.434us 1 1 100.00
lc_ctrl_security_escalation 7.530s 5624.369us 1 1 100.00
lc_ctrl_jtag_state_failure 32.820s 5590.282us 1 1 100.00
lc_ctrl_jtag_prog_failure 15.340s 2934.634us 1 1 100.00
lc_ctrl_jtag_errors 34.950s 15097.726us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 4.320s 176.292us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.040s 238.074us 1 1 100.00
lc_ctrl_jtag_prog_failure 15.340s 2934.634us 1 1 100.00
lc_ctrl_jtag_errors 34.950s 15097.726us 1 1 100.00
lc_ctrl_jtag_access 4.130s 903.307us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 15.080s 567.492us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.100s 1153.692us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.250s 268.213us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 5.620s 5789.910us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 7.810s 4136.409us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.530s 139.840us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.690s 230.589us 1 1 100.00
lc_ctrl_jtag_alert_test 1.310s 461.644us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 7.610s 2948.761us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.170s 54.024us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 27.000s 2866.115us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.050s 21.316us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.980s 86.263us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.980s 86.263us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.060s 53.565us 1 1 100.00
lc_ctrl_csr_rw 1.190s 208.870us 1 1 100.00
lc_ctrl_csr_aliasing 1.400s 18.092us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.410s 64.558us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.060s 53.565us 1 1 100.00
lc_ctrl_csr_rw 1.190s 208.870us 1 1 100.00
lc_ctrl_csr_aliasing 1.400s 18.092us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.410s 64.558us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.940s 224.787us 1 1 100.00
lc_ctrl_tl_intg_err 3.110s 234.237us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 3.110s 234.237us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 5.560s 217.722us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 8.420s 672.189us 1 1 100.00
lc_ctrl_sec_cm 6.940s 224.787us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 8.420s 672.189us 1 1 100.00
lc_ctrl_sec_cm 6.940s 224.787us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.420s 672.189us 1 1 100.00
lc_ctrl_sec_cm 6.940s 224.787us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.420s 672.189us 1 1 100.00
lc_ctrl_sec_cm 6.940s 224.787us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 8.420s 672.189us 1 1 100.00
lc_ctrl_sec_cm 6.940s 224.787us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.420s 672.189us 1 1 100.00
lc_ctrl_sec_cm 6.940s 224.787us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.420s 672.189us 1 1 100.00
lc_ctrl_sec_cm 6.940s 224.787us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 8.420s 672.189us 1 1 100.00
lc_ctrl_sec_cm 6.940s 224.787us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 7.530s 5624.369us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 5.530s 59.724us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.040s 238.074us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 9.290s 1717.093us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 9.290s 1717.093us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 7.140s 1180.090us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.340s 1552.702us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.340s 1552.702us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 15.370s 19193.113us 1 1 100.00