Simulation Results: lc_ctrl/volatile_unlock_enabled

 
17/04/2026 01:26:32 DVSim: v1.31.0 sha: ee0af46 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.95 %
  • code
  • 84.42 %
  • assert
  • 94.13 %
  • func
  • 94.31 %
  • line
  • 97.24 %
  • branch
  • 93.92 %
  • cond
  • 79.56 %
  • toggle
  • 85.97 %
  • FSM
  • 65.42 %
Validation stages
V1
100.00%
V2
96.67%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.620s 212.362us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.010s 15.948us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.820s 43.174us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.470s 39.715us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.860s 29.109us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.140s 59.914us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.820s 43.174us 1 1 100.00
lc_ctrl_csr_aliasing 0.860s 29.109us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 5.670s 56.357us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 4.780s 561.388us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.070s 24.109us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.230s 84.688us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.280s 915.377us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 7.270s 287.846us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 7.280s 915.377us 1 1 100.00
lc_ctrl_prog_failure 2.230s 84.688us 1 1 100.00
lc_ctrl_errors 7.270s 287.846us 1 1 100.00
lc_ctrl_security_escalation 5.210s 716.458us 1 1 100.00
lc_ctrl_jtag_state_failure 33.220s 1477.925us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.200s 87.718us 1 1 100.00
lc_ctrl_jtag_errors 47.030s 18126.813us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 1.860s 96.096us 1 1 100.00
lc_ctrl_jtag_state_post_trans 21.200s 3916.618us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.200s 87.718us 1 1 100.00
lc_ctrl_jtag_errors 47.030s 18126.813us 1 1 100.00
lc_ctrl_jtag_access 3.100s 285.075us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 13.540s 3219.191us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.210s 222.363us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.700s 372.383us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 7.760s 1666.065us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.300s 4035.222us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 0.930s 16.970us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.630s 90.379us 1 1 100.00
lc_ctrl_jtag_alert_test 0.950s 74.573us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 7.680s 7680.899us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.930s 20.307us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 5.000s 238.814us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.900s 348.368us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.380s 155.063us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.380s 155.063us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.010s 15.948us 1 1 100.00
lc_ctrl_csr_rw 0.820s 43.174us 1 1 100.00
lc_ctrl_csr_aliasing 0.860s 29.109us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.210s 31.244us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.010s 15.948us 1 1 100.00
lc_ctrl_csr_rw 0.820s 43.174us 1 1 100.00
lc_ctrl_csr_aliasing 0.860s 29.109us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.210s 31.244us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 9.240s 126.839us 1 1 100.00
lc_ctrl_tl_intg_err 1.660s 203.116us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.660s 203.116us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 4.780s 561.388us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.280s 915.377us 1 1 100.00
lc_ctrl_sec_cm 9.240s 126.839us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.280s 915.377us 1 1 100.00
lc_ctrl_sec_cm 9.240s 126.839us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.280s 915.377us 1 1 100.00
lc_ctrl_sec_cm 9.240s 126.839us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.280s 915.377us 1 1 100.00
lc_ctrl_sec_cm 9.240s 126.839us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.280s 915.377us 1 1 100.00
lc_ctrl_sec_cm 9.240s 126.839us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.280s 915.377us 1 1 100.00
lc_ctrl_sec_cm 9.240s 126.839us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.280s 915.377us 1 1 100.00
lc_ctrl_sec_cm 9.240s 126.839us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.280s 915.377us 1 1 100.00
lc_ctrl_sec_cm 9.240s 126.839us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.210s 716.458us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 5.670s 56.357us 1 1 100.00
lc_ctrl_jtag_state_post_trans 21.200s 3916.618us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 11.190s 1303.341us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 11.190s 1303.341us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 10.030s 1411.068us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 8.240s 574.755us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 8.240s 574.755us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 2.700s 287.222us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*])
lc_ctrl_stress_all 88698656040496927372362594647112708477350365094037987098959492938503867719460 2561
UVM_INFO @ 238813808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---