Simulation Results: otbn

 
17/04/2026 01:26:32 DVSim: v1.31.0 sha: ee0af46 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.10 %
  • code
  • 95.25 %
  • assert
  • 89.60 %
  • func
  • 97.46 %
  • block
  • 99.39 %
  • line
  • 99.58 %
  • branch
  • 92.26 %
  • toggle
  • 91.72 %
  • FSM
  • 97.44 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 9.000s 186.434us 1 1 100.00
single_binary 1 1 100.00
otbn_single 13.000s 113.279us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 27.000s 17.472us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 24.000s 72.814us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 28.000s 137.495us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 27.000s 44.030us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 33.000s 57.702us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 24.000s 72.814us 1 1 100.00
otbn_csr_aliasing 27.000s 44.030us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 56.000s 1871.170us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 42.000s 1329.576us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 27.000s 79.724us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 43.000s 326.880us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 217.000s 15613.944us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 36.000s 375.519us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 8.000s 83.623us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 6.000s 47.943us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 12.000s 113.687us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 27.000s 29.903us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 3.000s 14.152us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 7.000s 34.612us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 7.000s 34.612us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 27.000s 17.472us 1 1 100.00
otbn_csr_rw 24.000s 72.814us 1 1 100.00
otbn_csr_aliasing 27.000s 44.030us 1 1 100.00
otbn_same_csr_outstanding 4.000s 35.639us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 27.000s 17.472us 1 1 100.00
otbn_csr_rw 24.000s 72.814us 1 1 100.00
otbn_csr_aliasing 27.000s 44.030us 1 1 100.00
otbn_same_csr_outstanding 4.000s 35.639us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 8.000s 65.766us 1 1 100.00
otbn_dmem_err 17.000s 31.995us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 31.000s 44.699us 1 1 100.00
otbn_controller_ispr_rdata_err 30.000s 184.814us 1 1 100.00
otbn_mac_bignum_acc_err 7.000s 434.938us 1 1 100.00
otbn_urnd_err 5.000s 31.702us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 5.000s 31.615us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 6.000s 19.497us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 5.000s 16.027us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 388.000s 2467.189us 1 1 100.00
otbn_tl_intg_err 9.000s 356.972us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 21.000s 94.434us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 388.000s 2467.189us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 388.000s 2467.189us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 9.000s 186.434us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 17.000s 31.995us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 8.000s 65.766us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 9.000s 356.972us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 8.000s 83.623us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 8.000s 65.766us 1 1 100.00
otbn_dmem_err 17.000s 31.995us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 47.943us 1 1 100.00
otbn_illegal_mem_acc 5.000s 31.615us 1 1 100.00
otbn_sec_cm 388.000s 2467.189us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 388.000s 2467.189us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 13.000s 113.279us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 8.000s 65.766us 1 1 100.00
otbn_dmem_err 17.000s 31.995us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 47.943us 1 1 100.00
otbn_illegal_mem_acc 5.000s 31.615us 1 1 100.00
otbn_sec_cm 388.000s 2467.189us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 388.000s 2467.189us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 8.000s 83.623us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 8.000s 65.766us 1 1 100.00
otbn_dmem_err 17.000s 31.995us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 47.943us 1 1 100.00
otbn_illegal_mem_acc 5.000s 31.615us 1 1 100.00
otbn_sec_cm 388.000s 2467.189us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 388.000s 2467.189us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 13.000s 113.279us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 17.000s 25.011us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 6.000s 70.592us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 117.000s 798.585us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 117.000s 798.585us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 7.000s 37.212us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 388.000s 2467.189us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 388.000s 2467.189us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 8.000s 65.947us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 388.000s 2467.189us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 388.000s 2467.189us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 25.000s 120.226us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 25.000s 120.226us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 10.000s 31.819us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 13.000s 113.279us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 13.000s 113.279us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 13.000s 113.279us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 217.000s 15613.944us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 13.000s 113.279us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 13.000s 113.279us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 9.000s 22.701us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 13.000s 113.279us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 388.000s 2467.189us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 4.000s 6.950us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 7.000s 30.739us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
otbn_stress_all_with_rand_reset 3294518543017624694916923567918007871718276150839482207368212942467461537765 158
UVM_INFO @ 6950051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---