Simulation Results: otp_ctrl

 
17/04/2026 01:26:32 DVSim: v1.31.0 sha: ee0af46 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.45 %
  • code
  • 78.27 %
  • assert
  • 93.60 %
  • func
  • 72.48 %
  • line
  • 88.65 %
  • branch
  • 83.31 %
  • cond
  • 90.32 %
  • toggle
  • 85.17 %
  • FSM
  • 43.92 %
Validation stages
V1
100.00%
V2
85.00%
V2S
77.78%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.510s 190.920us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 8.010s 385.188us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 1.730s 75.497us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.540s 167.882us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 2.950s 88.697us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 3.240s 386.906us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.280s 281.056us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.540s 167.882us 1 1 100.00
otp_ctrl_csr_aliasing 3.240s 386.906us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.240s 148.325us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.160s 64.313us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 13.020s 314.691us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 2.990s 244.935us 1 1 100.00
partition_check 0 2 0.00
otp_ctrl_background_chks 27.800s 27448.092us 0 1 0.00
otp_ctrl_check_fail 1.720s 113.975us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 9.630s 1179.687us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 14.160s 1511.914us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 10.370s 5968.781us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 12.180s 966.634us 1 1 100.00
otp_ctrl_parallel_lc_esc 22.530s 13831.469us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 4.770s 270.537us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 2.230s 318.430us 0 1 0.00
test_access 1 1 100.00
otp_ctrl_test_access 11.590s 4158.766us 1 1 100.00
stress_all 1 1 100.00
otp_ctrl_stress_all 90.420s 15762.412us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.780s 40.633us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.950s 46.052us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 3.070s 149.193us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 3.070s 149.193us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.730s 75.497us 1 1 100.00
otp_ctrl_csr_rw 1.540s 167.882us 1 1 100.00
otp_ctrl_csr_aliasing 3.240s 386.906us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.010s 107.954us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.730s 75.497us 1 1 100.00
otp_ctrl_csr_rw 1.540s 167.882us 1 1 100.00
otp_ctrl_csr_aliasing 3.240s 386.906us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.010s 107.954us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 128.770s 41832.127us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 128.770s 41832.127us 1 1 100.00
otp_ctrl_tl_intg_err 16.370s 10453.475us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 128.770s 41832.127us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 128.770s 41832.127us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 16.370s 10453.475us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 8.010s 385.188us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 8.010s 385.188us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 128.770s 41832.127us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 128.770s 41832.127us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 128.770s 41832.127us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 128.770s 41832.127us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 128.770s 41832.127us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 128.770s 41832.127us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 128.770s 41832.127us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 128.770s 41832.127us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 128.770s 41832.127us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 128.770s 41832.127us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 128.770s 41832.127us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 128.770s 41832.127us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 128.770s 41832.127us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 128.770s 41832.127us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 128.770s 41832.127us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 22.530s 13831.469us 1 1 100.00
otp_ctrl_sec_cm 128.770s 41832.127us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 22.530s 13831.469us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 22.530s 13831.469us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 22.530s 13831.469us 1 1 100.00
otp_ctrl_macro_errs 2.230s 318.430us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 22.530s 13831.469us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 22.530s 13831.469us 1 1 100.00
otp_ctrl_sec_cm 128.770s 41832.127us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 22.530s 13831.469us 1 1 100.00
otp_ctrl_sec_cm 128.770s 41832.127us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 22.530s 13831.469us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 22.530s 13831.469us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 22.530s 13831.469us 1 1 100.00
otp_ctrl_macro_errs 2.230s 318.430us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 22.530s 13831.469us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 22.530s 13831.469us 1 1 100.00
otp_ctrl_sec_cm 128.770s 41832.127us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 2.990s 244.935us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 1.720s 113.975us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 14.160s 1511.914us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 14.160s 1511.914us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 14.160s 1511.914us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 14.160s 1511.914us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 14.160s 1511.914us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 8.010s 385.188us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 14.160s 1511.914us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 8.010s 385.188us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 128.770s 41832.127us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 9.630s 1179.687us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 8.010s 385.188us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 8.010s 385.188us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 2.230s 318.430us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 10.120s 5953.785us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 1.100s 45.882us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1315) [otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_check_error does not trigger!
otp_ctrl_background_chks 58940231230491920850950277760347646043507475179594026546267017943456182040031 18106
UVM_INFO @ 27448092293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_*
otp_ctrl_check_fail 49766626038368992874295251331123198507648540857073407402321352173114028496893 903
UVM_INFO @ 113975207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:691) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: OtpErr
otp_ctrl_macro_errs 111947914678121631798241541003481588975805777523823278769584011627191195037953 273
UVM_INFO @ 318430238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = *
otp_ctrl_stress_all_with_rand_reset 27519007111455573555357121122778929308176229018681045843901700694569611570021 93
UVM_INFO @ 45882141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---