Simulation Results: pattgen

 
17/04/2026 01:26:32 DVSim: v1.31.0 sha: ee0af46 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.08 %
  • code
  • 98.87 %
  • assert
  • 96.95 %
  • func
  • 89.42 %
  • block
  • 100.00 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • toggle
  • 96.61 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
0.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pattgen_smoke 2.000s 494.508us 1 1 100.00
csr_hw_reset 1 1 100.00
pattgen_csr_hw_reset 1.000s 18.025us 1 1 100.00
csr_rw 1 1 100.00
pattgen_csr_rw 1.000s 12.918us 1 1 100.00
csr_bit_bash 1 1 100.00
pattgen_csr_bit_bash 3.000s 348.362us 1 1 100.00
csr_aliasing 1 1 100.00
pattgen_csr_aliasing 2.000s 50.692us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pattgen_csr_mem_rw_with_rand_reset 2.000s 51.124us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pattgen_csr_rw 1.000s 12.918us 1 1 100.00
pattgen_csr_aliasing 2.000s 50.692us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
perf 0 1 0.00
pattgen_perf 0.000s 0.000us 0 1 0.00
cnt_rollover 1 1 100.00
cnt_rollover 12.000s 6968.299us 1 1 100.00
error 1 1 100.00
pattgen_error 1.000s 17.577us 1 1 100.00
stress_all 1 1 100.00
pattgen_stress_all 10.000s 187.009us 1 1 100.00
alert_test 1 1 100.00
pattgen_alert_test 1.000s 27.762us 1 1 100.00
intr_test 1 1 100.00
pattgen_intr_test 1.000s 18.472us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pattgen_tl_errors 1.000s 216.539us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pattgen_tl_errors 1.000s 216.539us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 18.025us 1 1 100.00
pattgen_csr_rw 1.000s 12.918us 1 1 100.00
pattgen_csr_aliasing 2.000s 50.692us 1 1 100.00
pattgen_same_csr_outstanding 2.000s 119.318us 1 1 100.00
tl_d_partial_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 18.025us 1 1 100.00
pattgen_csr_rw 1.000s 12.918us 1 1 100.00
pattgen_csr_aliasing 2.000s 50.692us 1 1 100.00
pattgen_same_csr_outstanding 2.000s 119.318us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pattgen_tl_intg_err 1.000s 96.432us 1 1 100.00
pattgen_sec_cm 1.000s 179.768us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pattgen_tl_intg_err 1.000s 96.432us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
pattgen_stress_all_with_rand_reset 15.000s 6938.764us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
pattgen_inactive_level 68.000s 10183.239us 0 1 0.00

Error Messages

   Test seed line log context
Job killed!
pattgen_perf 6353582099176223273542939439482628985282754849265830442016774816550188278857 None
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=22)
pattgen_inactive_level 108621424421679382367558143443401216435921232422777554181856198734696062997636 99
UVM_INFO @ 10183238840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
pattgen_stress_all_with_rand_reset 53918230653511407387889358610869006629617973492056240030223575381488496009922 212
UVM_ERROR @ 6527918048 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 6527918048 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 4/5
UVM_INFO @ 6528148817 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]