Simulation Results: pwm

 
17/04/2026 01:26:32 DVSim: v1.31.0 sha: ee0af46 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.72 %
  • code
  • 96.07 %
  • assert
  • 95.40 %
  • func
  • 98.68 %
  • block
  • 99.02 %
  • line
  • 99.28 %
  • branch
  • 98.27 %
  • toggle
  • 90.65 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwm_smoke 4.000s 514.216us 1 1 100.00
csr_hw_reset 1 1 100.00
pwm_csr_hw_reset 1.000s 26.595us 1 1 100.00
csr_rw 1 1 100.00
pwm_csr_rw 1.000s 25.617us 1 1 100.00
csr_bit_bash 1 1 100.00
pwm_csr_bit_bash 5.000s 1012.502us 1 1 100.00
csr_aliasing 1 1 100.00
pwm_csr_aliasing 2.000s 180.461us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwm_csr_mem_rw_with_rand_reset 1.000s 96.122us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwm_csr_rw 1.000s 25.617us 1 1 100.00
pwm_csr_aliasing 2.000s 180.461us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dutycycle 1 1 100.00
pwm_rand_output 34.000s 10827.119us 1 1 100.00
pulse 1 1 100.00
pwm_rand_output 34.000s 10827.119us 1 1 100.00
blink 1 1 100.00
pwm_rand_output 34.000s 10827.119us 1 1 100.00
heartbeat 1 1 100.00
pwm_rand_output 34.000s 10827.119us 1 1 100.00
resolution 1 1 100.00
pwm_rand_output 34.000s 10827.119us 1 1 100.00
multi_channel 1 1 100.00
pwm_rand_output 34.000s 10827.119us 1 1 100.00
polarity 1 1 100.00
pwm_rand_output 34.000s 10827.119us 1 1 100.00
phase 2 2 100.00
pwm_rand_output 34.000s 10827.119us 1 1 100.00
pwm_phase 31.000s 13639.085us 1 1 100.00
lowpower 1 1 100.00
pwm_rand_output 34.000s 10827.119us 1 1 100.00
perf 1 1 100.00
pwm_perf 31.000s 158573.893us 1 1 100.00
regwen 0 1 0.00
pwm_regwen 137.000s 7353.965us 0 1 0.00
stress_all 1 1 100.00
pwm_stress_all 53.000s 31729.142us 1 1 100.00
alert_test 1 1 100.00
pwm_alert_test 1.000s 17.666us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwm_tl_errors 2.000s 70.620us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwm_tl_errors 2.000s 70.620us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwm_csr_hw_reset 1.000s 26.595us 1 1 100.00
pwm_csr_rw 1.000s 25.617us 1 1 100.00
pwm_csr_aliasing 2.000s 180.461us 1 1 100.00
pwm_same_csr_outstanding 1.000s 159.533us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwm_csr_hw_reset 1.000s 26.595us 1 1 100.00
pwm_csr_rw 1.000s 25.617us 1 1 100.00
pwm_csr_aliasing 2.000s 180.461us 1 1 100.00
pwm_same_csr_outstanding 1.000s 159.533us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pwm_tl_intg_err 3.000s 437.402us 1 1 100.00
pwm_sec_cm 2.000s 46.704us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pwm_tl_intg_err 3.000s 437.402us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
heartbeat_wrap 1 1 100.00
pwm_heartbeat_wrap 28.000s 131245.491us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:217) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr pwm_reg_block.invert (addr=*)
pwm_regwen 14871169067788189627114294496926453685166548879954376780574044839374209595503 111
UVM_INFO @ 7353964805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---