Simulation Results: pwrmgr

 
17/04/2026 01:26:32 DVSim: v1.31.0 sha: ee0af46 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.23 %
  • code
  • 94.56 %
  • assert
  • 96.08 %
  • func
  • 95.06 %
  • line
  • 98.92 %
  • branch
  • 95.42 %
  • cond
  • 94.63 %
  • toggle
  • 89.83 %
  • FSM
  • 94.00 %
Validation stages
V1
100.00%
V2
93.33%
V2S
80.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.640s 25.170us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.710s 43.340us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.660s 86.919us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.430s 80.688us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 1.320s 137.667us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 1.040s 99.955us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.660s 86.919us 1 1 100.00
pwrmgr_csr_aliasing 1.320s 137.667us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 1.130s 201.017us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 1.130s 201.017us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.810s 103.041us 1 1 100.00
pwrmgr_lowpower_invalid 0.830s 91.066us 1 1 100.00
reset 2 2 100.00
pwrmgr_reset 0.690s 75.464us 1 1 100.00
pwrmgr_reset_invalid 0.850s 176.843us 1 1 100.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.690s 75.464us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 1.170s 135.056us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 1.200s 298.765us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 1.220s 99.008us 1 1 100.00
stress_all 0 1 0.00
pwrmgr_stress_all 19.120s 11272.388us 0 1 0.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.660s 193.574us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.430s 89.199us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.430s 89.199us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.710s 43.340us 1 1 100.00
pwrmgr_csr_rw 0.660s 86.919us 1 1 100.00
pwrmgr_csr_aliasing 1.320s 137.667us 1 1 100.00
pwrmgr_same_csr_outstanding 0.730s 28.282us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.710s 43.340us 1 1 100.00
pwrmgr_csr_rw 0.660s 86.919us 1 1 100.00
pwrmgr_csr_aliasing 1.320s 137.667us 1 1 100.00
pwrmgr_same_csr_outstanding 0.730s 28.282us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
pwrmgr_tl_intg_err 0.720s 8.363us 0 1 0.00
pwrmgr_sec_cm 0.810s 36.303us 0 1 0.00
prim_count_check 0 1 0.00
pwrmgr_sec_cm 0.810s 36.303us 0 1 0.00
prim_fsm_check 0 1 0.00
pwrmgr_sec_cm 0.810s 36.303us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
pwrmgr_tl_intg_err 0.720s 8.363us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.660s 1058.223us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 1 1 100.00
pwrmgr_wakeup_reset 1.170s 135.056us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.850s 84.344us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.760s 28.751us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 0 1 0.00
pwrmgr_sec_cm 0.810s 36.303us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
pwrmgr_sec_cm 0.810s 36.303us 0 1 0.00
sec_cm_fsm_terminal 0 1 0.00
pwrmgr_sec_cm 0.810s 36.303us 0 1 0.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.780s 92.489us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.630s 47.068us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.850s 134.412us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.660s 86.919us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.660s 86.919us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 0 1 0.00
pwrmgr_escalation_timeout 0.750s 971.113us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 2.930s 9117.356us 1 1 100.00

Error Messages

   Test seed line log context
Offending '((!clk_en) || status)'
pwrmgr_escalation_timeout 33157782830932122674435809864540230513242509402626284733146935990970919603853 79
UVM_ERROR @ 971112664 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 971112664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [pwrmgr_common_vseq] expect alert:fatal_fault to fire
pwrmgr_tl_intg_err 89807209257445932332753491292804748704914703223861423083187126205271715715621 78
UVM_INFO @ 8362638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_sec_cm 72429577265673047530794419315951589656742262269461533519722660593947824662168 85
UVM_INFO @ 36303174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_vseq.sv:62) [pwrmgr_reset_vseq] wait timeout occurred!
pwrmgr_stress_all 16876948417843055287049719268655578007912362877485174101384443493993823159309 1848
UVM_INFO @ 11272388104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---